diff options
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mbus.h | 61 | ||||
| -rw-r--r-- | include/linux/mtd/nand.h | 3 | ||||
| -rw-r--r-- | include/linux/phy.h | 14 |
3 files changed, 77 insertions, 1 deletions
diff --git a/include/linux/mbus.h b/include/linux/mbus.h new file mode 100644 index 0000000000..578ff33146 --- /dev/null +++ b/include/linux/mbus.h @@ -0,0 +1,61 @@ +/* + * Marvell MBUS common definitions. + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __LINUX_MBUS_H +#define __LINUX_MBUS_H + +struct resource; + +struct mbus_dram_target_info { + /* + * The 4-bit MBUS target ID of the DRAM controller. + */ + u8 mbus_dram_target_id; + + /* + * The base address, size, and MBUS attribute ID for each + * of the possible DRAM chip selects. Peripherals are + * required to support at least 4 decode windows. + */ + int num_cs; + struct mbus_dram_window { + u8 cs_index; + u8 mbus_attr; + u32 base; + u32 size; + } cs[4]; +}; + +/* Flags for PCI/PCIe address decoding regions */ +#define MVEBU_MBUS_PCI_IO 0x1 +#define MVEBU_MBUS_PCI_MEM 0x2 +#define MVEBU_MBUS_PCI_WA 0x3 + +/* + * Magic value that explicits that we don't need a remapping-capable + * address decoding window. + */ +#define MVEBU_MBUS_NO_REMAP (0xffffffff) + +/* Maximum size of a mbus window name */ +#define MVEBU_MBUS_MAX_WINNAME_SZ 32 + +const struct mbus_dram_target_info *mvebu_mbus_dram_info(void); +void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); +void mvebu_mbus_get_pcie_io_aperture(struct resource *res); +int mvebu_mbus_add_window_remap_by_id(unsigned int target, + unsigned int attribute, + phys_addr_t base, size_t size, + phys_addr_t remap); +int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, + phys_addr_t base, size_t size); +int mvebu_mbus_del_window(phys_addr_t base, size_t size); + +#endif /* __LINUX_MBUS_H */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 74ea0b4e02..3c7509f9af 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -162,7 +162,8 @@ typedef enum { #define NAND_ROM 0x00000800 /* Device supports subpage reads */ -#define NAND_SUBPAGE_READ 0x00001000 +/* Disabled in barebox for smaller binary sizes */ +#define NAND_SUBPAGE_READ (__BAREBOX__ ? 0x0 : 0x00001000) /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG diff --git a/include/linux/phy.h b/include/linux/phy.h index c8980b0191..9567c43e38 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -280,6 +280,20 @@ int phy_device_connect(struct eth_device *dev, struct mii_bus *bus, int addr, void (*adjust_link) (struct eth_device *edev), u32 flags, phy_interface_t interface); +#if defined(CONFIG_OFTREE) +int of_phy_device_connect(struct eth_device *edev, struct device_node *phy_np, + void (*adjust_link) (struct eth_device *edev), + u32 flags, phy_interface_t interface); +#else +static inline int of_phy_device_connect(struct eth_device *edev, + struct device_node *phy_np, + void (*adjust_link) (struct eth_device *edev), + u32 flags, phy_interface_t interface) +{ + return -ENOSYS; +} +#endif + int phy_update_status(struct phy_device *phydev); int phy_wait_aneg_done(struct phy_device *phydev); |