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-rw-r--r--include/mci.h203
1 files changed, 173 insertions, 30 deletions
diff --git a/include/mci.h b/include/mci.h
index 2098b4fbf0..52bf84ecdb 100644
--- a/include/mci.h
+++ b/include/mci.h
@@ -51,6 +51,11 @@
#define MMC_CAP_SD_HIGHSPEED (1 << 3)
#define MMC_CAP_MMC_HIGHSPEED (1 << 4)
#define MMC_CAP_MMC_HIGHSPEED_52MHZ (1 << 5)
+#define MMC_CAP_MMC_3_3V_DDR (1 << 7) /* Host supports eMMC DDR 3.3V */
+#define MMC_CAP_MMC_1_8V_DDR (1 << 8) /* Host supports eMMC DDR 1.8V */
+#define MMC_CAP_MMC_1_2V_DDR (1 << 9) /* Host supports eMMC DDR 1.2V */
+#define MMC_CAP_DDR (MMC_CAP_MMC_3_3V_DDR | MMC_CAP_MMC_1_8V_DDR | \
+ MMC_CAP_MMC_1_2V_DDR)
/* Mask of all caps for bus width */
#define MMC_CAP_BIT_DATA_MASK (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)
@@ -77,6 +82,8 @@
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
+#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
#define MMC_CMD_WRITE_SINGLE_BLOCK 24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
#define MMC_CMD_APP_CMD 55
@@ -91,6 +98,8 @@
#define SD_CMD_APP_SEND_OP_COND 41
#define SD_CMD_APP_SEND_SCR 51
+#define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */
+
/* SCR definitions in different words */
#define SD_HIGHSPEED_BUSY 0x00020000
#define SD_HIGHSPEED_SUPPORTED 0x00020000
@@ -286,19 +295,34 @@
#define EXT_CSD_CARD_TYPE_MASK 0x3f
#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_26 | \
+ EXT_CSD_CARD_TYPE_52)
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
/* DDR mode @1.8V or 3V I/O */
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
/* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_SDR_1_8V (1<<4) /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_SDR_1_2V (1<<5) /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
/* SDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
+ EXT_CSD_CARD_TYPE_HS200_1_2V)
+#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
+#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
+#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
+ EXT_CSD_CARD_TYPE_HS400_1_2V)
+#define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */
/* register PARTITIONS_ATTRIBUTE [156] */
#define EXT_CSD_ENH_USR_MASK (1 << 0)
/* register PARTITIONING_SUPPORT [160] */
-#define EXT_CSD_ENH_ATTRIBUTE_EN_MASK (1 << 0)
+#define EXT_CSD_ENH_ATTRIBUTE_EN_MASK (1 << 1)
+
+/* register EXT_CSD_WR_REL_PARAM [166] */
+#define EXT_CSD_HS_CTRL_REL (1 << 0)
+#define EXT_CSD_EN_REL_WR (1 << 2)
/* register BUS_WIDTH [183], field Bus Mode Selection [4:0] */
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
@@ -306,10 +330,33 @@
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
+#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
+
+#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
+#define EXT_CSD_TIMING_HS 1 /* High speed */
+#define EXT_CSD_TIMING_HS200 2 /* HS200 */
+#define EXT_CSD_TIMING_HS400 3 /* HS400 */
+#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
#define R1_ILLEGAL_COMMAND (1 << 22)
+#define R1_STATUS(x) (x & 0xFFF9A000)
+#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
+#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
+#define R1_SWITCH_ERROR (1 << 7)
#define R1_APP_CMD (1 << 5)
+#define R1_STATUS_MASK (~0x0206BF7F)
+
+#define R1_STATE_IDLE 0
+#define R1_STATE_READY 1
+#define R1_STATE_IDENT 2
+#define R1_STATE_STBY 3
+#define R1_STATE_TRAN 4
+#define R1_STATE_DATA 5
+#define R1_STATE_RCV 6
+#define R1_STATE_PRG 7
+#define R1_STATE_DIS 8
+
#define R1_SPI_IDLE (1 << 0)
#define R1_SPI_ERASE_RESET (1 << 1)
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
@@ -326,6 +373,17 @@
#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
+#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */
+#define MMC_CMD_AC (0 << 5)
+#define MMC_CMD_ADTC (1 << 5)
+#define MMC_CMD_BC (2 << 5)
+#define MMC_CMD_BCR (3 << 5)
+
+#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */
+#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */
+#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */
+#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */
+
#define MMC_RSP_NONE (0)
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
@@ -336,6 +394,19 @@
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+/*
+ * These are the SPI response types for MMC, SD, and SDIO cards.
+ * Commands return R1, with maybe more info. Zero is an error type;
+ * callers must always provide the appropriate MMC_RSP_SPI_Rx flags.
+ */
+#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1)
+#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY)
+#define MMC_RSP_SPI_R2 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2)
+#define MMC_RSP_SPI_R3 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4)
+#define MMC_RSP_SPI_R4 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4)
+#define MMC_RSP_SPI_R5 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2)
+#define MMC_RSP_SPI_R7 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4)
+
/** command information to be sent to the SD/MMC card */
struct mci_cmd {
unsigned cmdidx; /**< Command to be sent to the SD/MMC card */
@@ -359,58 +430,100 @@ enum mci_timing {
MMC_TIMING_LEGACY = 0,
MMC_TIMING_MMC_HS = 1,
MMC_TIMING_SD_HS = 2,
- MMC_TIMING_UHS_SDR12 = MMC_TIMING_LEGACY,
- MMC_TIMING_UHS_SDR25 = MMC_TIMING_SD_HS,
- MMC_TIMING_UHS_SDR50 = 3,
- MMC_TIMING_UHS_SDR104 = 4,
- MMC_TIMING_UHS_DDR50 = 5,
- MMC_TIMING_MMC_HS200 = 6,
- MMC_TIMING_MMC_DDR52 = 7,
- MMC_TIMING_MMC_HS400 = 8,
+ MMC_TIMING_UHS_SDR12 = 3,
+ MMC_TIMING_UHS_SDR25 = 4,
+ MMC_TIMING_UHS_SDR50 = 5,
+ MMC_TIMING_UHS_SDR104 = 6,
+ MMC_TIMING_UHS_DDR50 = 7,
+ MMC_TIMING_MMC_DDR52 = 8,
+ MMC_TIMING_MMC_HS200 = 9,
+ MMC_TIMING_MMC_HS400 = 10,
+ MMC_TIMING_SD_EXP = 11,
+ MMC_TIMING_SD_EXP_1_2V = 12,
};
-struct mci_ios {
- unsigned int clock; /* clock rate */
-
- unsigned char bus_width; /* data bus width */
-
-#define MMC_BUS_WIDTH_1 0
-#define MMC_BUS_WIDTH_4 2
-#define MMC_BUS_WIDTH_8 3
+static inline bool mci_timing_is_ddr(enum mci_timing timing)
+{
+ switch (timing) {
+ case MMC_TIMING_UHS_DDR50:
+ case MMC_TIMING_MMC_HS200:
+ case MMC_TIMING_MMC_DDR52:
+ case MMC_TIMING_MMC_HS400:
+ return true;
+ default:
+ return false;
+ }
+}
- enum mci_timing timing; /* timing specification used */
+enum mci_bus_width {
+ MMC_BUS_WIDTH_1 = 0,
+ MMC_BUS_WIDTH_4 = 2,
+ MMC_BUS_WIDTH_8 = 3,
+};
-#define MMC_SDR_MODE 0
-#define MMC_1_2V_DDR_MODE 1
-#define MMC_1_8V_DDR_MODE 2
-#define MMC_1_2V_SDR_MODE 3
-#define MMC_1_8V_SDR_MODE 4
+struct mci_ios {
+ unsigned int clock; /* clock rate */
+ enum mci_bus_width bus_width; /* data bus width */
+ enum mci_timing timing; /* timing specification used */
};
struct mci;
/** host information */
struct mci_host {
- struct device_d *hw_dev; /**< the host MCI hardware device */
+ struct device *hw_dev; /**< the host MCI hardware device */
struct mci *mci;
const char *devname; /**< the devicename for the card, defaults to disk%d */
unsigned voltages;
unsigned host_caps; /**< Host's interface capabilities, refer MMC_VDD_* */
+ unsigned caps2; /* More host capabilities */
+#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
+#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */
+#define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND (1 << 3) /* Can do full power cycle in suspend */
+#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */
+#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */
+#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \
+ MMC_CAP2_HS200_1_2V_SDR)
+#define MMC_CAP2_SD_EXP (1 << 7) /* SD express via PCIe */
+#define MMC_CAP2_SD_EXP_1_2V (1 << 8) /* SD express 1.2V */
+#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */
+#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */
+#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */
+#define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */
+#define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */
+#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \
+ MMC_CAP2_HS400_1_2V)
+#define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)
+#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
+#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
+#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */
+#define MMC_CAP2_NO_SDIO (1 << 19) /* Do not send SDIO commands during initialization */
+#define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */
+#define MMC_CAP2_NO_SD (1 << 21) /* Do not send SD commands during initialization */
+#define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */
+#define MMC_CAP2_CQE (1 << 23) /* Has eMMC command queue engine */
+#define MMC_CAP2_CQE_DCMD (1 << 24) /* CQE can issue a direct command */
+#define MMC_CAP2_AVOID_3_3V (1 << 25) /* Host must negotiate down from 3.3V */
+#define MMC_CAP2_MERGE_CAPABLE (1 << 26) /* Host can merge a segment over the segment size */
+#define MMC_CAP2_CRYPTO 0
unsigned f_min; /**< host interface lower limit */
unsigned f_max; /**< host interface upper limit */
unsigned clock; /**< Current clock used to talk to the card */
- unsigned bus_width; /**< used data bus width to the card */
+ unsigned actual_clock;
+ enum mci_bus_width bus_width; /**< used data bus width to the card */
enum mci_timing timing; /**< used timing specification to the card */
+ unsigned hs_max_dtr;
+ unsigned hs200_max_dtr;
unsigned max_req_size;
unsigned dsr_val; /**< optional dsr value */
int use_dsr; /**< optional dsr usage flag */
+ int broken_cd; /**< card detect is broken */
bool non_removable; /**< device is non removable */
- bool no_sd; /**< do not send SD commands during initialization */
bool disable_wp; /**< ignore write-protect detection logic */
struct regulator *supply;
/** init the host interface */
- int (*init)(struct mci_host*, struct device_d*);
+ int (*init)(struct mci_host*, struct device*);
/** change host interface settings */
void (*set_ios)(struct mci_host*, struct mci_ios *);
/** handle a command */
@@ -419,6 +532,8 @@ struct mci_host {
int (*card_present)(struct mci_host *);
/** check if a card is write protected */
int (*card_write_protected)(struct mci_host *);
+ /* The tuning command opcode value is different for SD and eMMC cards */
+ int (*execute_tuning)(struct mci_host *, u32);
};
#define MMC_NUM_BOOT_PARTITION 2
@@ -442,8 +557,9 @@ struct mci_part {
/** MMC/SD and interface instance information */
struct mci {
struct mci_host *host; /**< the host for this card */
- struct device_d dev; /**< the device for our disk (mcix) */
+ struct device dev; /**< the device for our disk (mcix) */
unsigned version;
+ bool sdio; /**< card is a SDIO card */
/** != 0 when a high capacity card is connected (OCR -> OCR_HCS) */
int high_capacity;
unsigned card_caps; /**< Card's capabilities */
@@ -483,6 +599,8 @@ void mci_of_parse_node(struct mci_host *host, struct device_node *np);
int mci_detect_card(struct mci_host *);
int mci_send_ext_csd(struct mci *mci, char *ext_csd);
int mci_switch(struct mci *mci, unsigned index, unsigned value);
+int mci_switch_status(struct mci *mci, bool crc_err_fatal);
+u8 *mci_get_ext_csd(struct mci *mci);
static inline int mmc_host_is_spi(struct mci_host *host)
{
@@ -499,4 +617,29 @@ static inline struct mci *mci_get_device_by_devpath(const char *devpath)
return mci_get_device_by_name(devpath_to_name(devpath));
}
+#define MMC_HIGH_26_MAX_DTR 26000000
+#define MMC_HIGH_52_MAX_DTR 52000000
+#define MMC_HIGH_DDR_MAX_DTR 52000000
+#define MMC_HS200_MAX_DTR 200000000
+
+static inline int mmc_card_hs(struct mci *mci)
+{
+ return mci->host->timing == MMC_TIMING_SD_HS ||
+ mci->host->timing == MMC_TIMING_MMC_HS;
+}
+
+/*
+ * Execute tuning sequence to seek the proper bus operating
+ * conditions for HS200 and HS400, which sends CMD21 to the device.
+ */
+int mmc_hs200_tuning(struct mci *mci);
+int mci_execute_tuning(struct mci *mci);
+int mci_send_abort_tuning(struct mci *mci, u32 opcode);
+int mmc_select_timing(struct mci *mci);
+
+static inline bool mmc_card_hs200(struct mci *mci)
+{
+ return mci->host->timing == MMC_TIMING_MMC_HS200;
+}
+
#endif /* _MCI_H_ */