diff options
Diffstat (limited to 'include/soc/fsl')
| -rw-r--r-- | include/soc/fsl/caam.h | 17 | ||||
| -rw-r--r-- | include/soc/fsl/fsl_ddr_sdram.h | 157 | ||||
| -rw-r--r-- | include/soc/fsl/fsl_fman.h | 3 | ||||
| -rw-r--r-- | include/soc/fsl/fsl_qbman.h | 18 | ||||
| -rw-r--r-- | include/soc/fsl/fsl_udc.h | 402 | ||||
| -rw-r--r-- | include/soc/fsl/immap_lsch2.h | 172 | ||||
| -rw-r--r-- | include/soc/fsl/immap_lsch3.h | 306 | ||||
| -rw-r--r-- | include/soc/fsl/scfg.h | 19 |
8 files changed, 964 insertions, 130 deletions
diff --git a/include/soc/fsl/caam.h b/include/soc/fsl/caam.h new file mode 100644 index 0000000000..a919a114e8 --- /dev/null +++ b/include/soc/fsl/caam.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +#ifndef __SOC_FSL_CAAM_H_ +#define __SOC_FSL_CAAM_H_ + +#include <linux/compiler.h> +#include <linux/types.h> + +struct caam_ctrl; + +int early_caam_init(struct caam_ctrl __iomem *caam, bool is_imx); + +static inline int imx_early_caam_init(struct caam_ctrl __iomem *caam) +{ + return early_caam_init(caam, true); +} + +#endif diff --git a/include/soc/fsl/fsl_ddr_sdram.h b/include/soc/fsl/fsl_ddr_sdram.h index 80508ef5d5..c20bc027fe 100644 --- a/include/soc/fsl/fsl_ddr_sdram.h +++ b/include/soc/fsl/fsl_ddr_sdram.h @@ -8,6 +8,7 @@ #define FSL_DDR_MEMCTL_H #include <ddr_spd.h> +#include <ddr_dimms.h> #include <soc/fsl/fsl_immap.h> struct common_timing_params { @@ -418,97 +419,6 @@ typedef struct memctl_options_s { #define EDC_ECC 2 #define EDC_AC_PARITY 4 -/* Parameters for a DDR dimm computed from the SPD */ -struct dimm_params { - - /* DIMM organization parameters */ - char mpart[19]; /* guaranteed null terminated */ - - unsigned int n_ranks; - unsigned int die_density; - unsigned long long rank_density; - unsigned long long capacity; - unsigned int data_width; - unsigned int primary_sdram_width; - unsigned int ec_sdram_width; - unsigned int registered_dimm; - unsigned int package_3ds; /* number of dies in 3DS DIMM */ - unsigned int device_width; /* x4, x8, x16 components */ - - /* SDRAM device parameters */ - unsigned int n_row_addr; - unsigned int n_col_addr; - unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ - unsigned int bank_addr_bits; /* DDR4 */ - unsigned int bank_group_bits; /* DDR4 */ - unsigned int n_banks_per_sdram_device; /* !DDR4 */ - unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ - - /* used in computing base address of DIMMs */ - unsigned long long base_address; - /* mirrored DIMMs */ - unsigned int mirrored_dimm; /* only for ddr3 */ - - /* DIMM timing parameters */ - - int mtb_ps; /* medium timebase ps */ - int ftb_10th_ps; /* fine timebase, in 1/10 ps */ - int taa_ps; /* minimum CAS latency time */ - int tfaw_ps; /* four active window delay */ - - /* - * SDRAM clock periods - * The range for these are 1000-10000 so a short should be sufficient - */ - int tckmin_x_ps; - int tckmin_x_minus_1_ps; - int tckmin_x_minus_2_ps; - int tckmax_ps; - - /* SPD-defined CAS latencies */ - unsigned int caslat_x; - unsigned int caslat_x_minus_1; - unsigned int caslat_x_minus_2; - - unsigned int caslat_lowest_derated; /* Derated CAS latency */ - - /* basic timing parameters */ - int trcd_ps; - int trp_ps; - int tras_ps; - - int trfc1_ps; /* DDR4 */ - int trfc2_ps; /* DDR4 */ - int trfc4_ps; /* DDR4 */ - int trrds_ps; /* DDR4 */ - int trrdl_ps; /* DDR4 */ - int tccdl_ps; /* DDR4 */ - int trfc_slr_ps; /* DDR4 */ - int twr_ps; /* !DDR4, maximum = 63750 ps */ - int trfc_ps; /* max = 255 ns + 256 ns + .75 ns - = 511750 ps */ - int trrd_ps; /* !DDR4, maximum = 63750 ps */ - int twtr_ps; /* !DDR4, maximum = 63750 ps */ - int trtp_ps; /* !DDR4, byte 38, spd->trtp */ - - int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - int refresh_rate_ps; - int extended_op_srt; - - int tis_ps; /* DDR1, DDR2, byte 32, spd->ca_setup */ - int tih_ps; /* DDR1, DDR2, byte 33, spd->ca_hold */ - int tds_ps; /* DDR1, DDR2, byte 34, spd->data_setup */ - int tdh_ps; /* DDR1, DDR2, byte 35, spd->data_hold */ - int tdqsq_max_ps; /* DDR1, DDR2, byte 44, spd->tdqsq */ - int tqhs_ps; /* DDR1, DDR2, byte 45, spd->tqhs */ - - /* DDR3 & DDR4 RDIMM */ - unsigned char rcw[16]; /* Register Control Word 0-15 */ - unsigned int dq_mapping[18]; /* DDR4 */ - unsigned int dq_mapping_ors; /* DDR4 */ -}; - struct fsl_ddr_controller { int num; unsigned long ddr_freq; @@ -539,21 +449,54 @@ struct fsl_ddr_info { unsigned long long mem_base; }; -phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo); -void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step); - -#ifdef CONFIG_SYS_FSL_DDR_LE -#define ddr_in32(a) in_le32(a) -#define ddr_out32(a, v) out_le32(a, v) -#define ddr_setbits32(a, v) setbits_le32(a, v) -#define ddr_clrbits32(a, v) clrbits_le32(a, v) -#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) -#else -#define ddr_in32(a) in_be32(a) -#define ddr_out32(a, v) out_be32(a, v) -#define ddr_setbits32(a, v) setbits_be32(a, v) -#define ddr_clrbits32(a, v) clrbits_be32(a, v) -#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) -#endif +phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo, bool little_endian); +void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step, bool little_endian); + +enum ddr_endianess { + DDR_ENDIANESS_LE, + DDR_ENDIANESS_BE, +}; + +extern enum ddr_endianess ddr_endianess; + +static inline u32 ddr_in32(void __iomem *reg) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + return in_le32(reg); + else + return in_be32(reg); +} + +static inline void ddr_out32(void __iomem *reg, u32 val) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + out_le32(reg, val); + else + out_be32(reg, val); +} + +static inline void ddr_setbits32(void __iomem *reg, u32 set) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + setbits_le32(reg, set); + else + setbits_be32(reg, set); +} + +static inline void ddr_clrbits32(void __iomem *reg, u32 clr) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + clrbits_le32(reg, clr); + else + clrbits_be32(reg, clr); +} + +static inline void ddr_clrsetbits32(void __iomem *reg, u32 clr, u32 set) +{ + if (ddr_endianess == DDR_ENDIANESS_LE) + clrsetbits_le32(reg, clr, set); + else + clrsetbits_be32(reg, clr, set); +} #endif diff --git a/include/soc/fsl/fsl_fman.h b/include/soc/fsl/fsl_fman.h index 96d61298ef..fd69fded38 100644 --- a/include/soc/fsl/fsl_fman.h +++ b/include/soc/fsl/fsl_fman.h @@ -348,6 +348,9 @@ struct fm_fpm { /* FPM Flush Control Register */ #define FMFP_FLC_DISP_LIM_NONE 0x00000000 /* no dispatch limitation */ +/* FMan Reset Command Register */ +#define FMFP_RSTC_RFM 0x80000000 /* FMan Soft Reset Command */ + /* FMFP_EE - FPM event and enable register */ #define FMFPEE_DECC 0x80000000 /* double ECC err on FPM ram */ #define FMFPEE_STL 0x40000000 /* stall of task ... */ diff --git a/include/soc/fsl/fsl_qbman.h b/include/soc/fsl/fsl_qbman.h index 4687eb9bb1..1caaf4808d 100644 --- a/include/soc/fsl/fsl_qbman.h +++ b/include/soc/fsl/fsl_qbman.h @@ -5,23 +5,9 @@ #ifndef __FSL_QBMAN_H__ #define __FSL_QBMAN_H__ -void fdt_fixup_qportals(void *blob); -void fdt_fixup_bportals(void *blob); -void inhibit_portals(void __iomem *addr, int max_portals, - int arch_max_portals, int portal_cinh_size); -void setup_qbman_portals(void); -struct ccsr_qman { -#ifdef CONFIG_SYS_FSL_QMAN_V3 +struct ccsr_qman_v3 { u8 res0[0x200]; -#else - struct { - u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ - u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ - u32 res; - u32 qcsp_dd_cfg; /* 0xc - SW Portal Dynamic Debug cfg */ - } qcsp[32]; -#endif /* Not actually reserved, but irrelevant to u-boot */ u8 res[0xbf8 - 0x200]; u32 ip_rev_1; @@ -46,14 +32,12 @@ struct ccsr_qman { u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ u8 res7[0x2e8]; -#ifdef CONFIG_SYS_FSL_QMAN_V3 struct { u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ u32 res; u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/ } qcsp[50]; -#endif }; struct ccsr_bman { diff --git a/include/soc/fsl/fsl_udc.h b/include/soc/fsl/fsl_udc.h new file mode 100644 index 0000000000..c1abe222ba --- /dev/null +++ b/include/soc/fsl/fsl_udc.h @@ -0,0 +1,402 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __FSL_UDC_H +#define __FSL_UDC_H + +#include <linux/types.h> +#include <io.h> + +/* USB DR device mode registers (Little Endian) */ +struct usb_dr_device { + /* Capability register */ + u8 res1[256]; /* 0x000 */ + u16 caplength; /* 0x100: Capability Register Length */ + u16 hciversion; /* 0x102: Host Controller Interface Version */ + u32 hcsparams; /* 0x104: Host Controller Structual Parameters */ + u32 hccparams; /* 0x108: Host Controller Capability Parameters */ + u8 res2[20]; /* 0x10c */ + u32 dciversion; /* 0x120: Device Controller Interface Version */ + u32 dccparams; /* 0x124: Device Controller Capability Parameters */ + u8 res3[24]; /* 0x128 */ + /* Operation register */ + u32 usbcmd; /* 0x140: USB Command Register */ + u32 usbsts; /* 0x144: USB Status Register */ + u32 usbintr; /* 0x148: USB Interrupt Enable Register */ + u32 frindex; /* 0x14c: Frame Index Register */ + u8 res4[4]; /* 0x150 */ + u32 deviceaddr; /* 0x154: Device Address */ + u32 endpointlistaddr; /* 0x158: Endpoint List Address Register */ + u8 res5[4]; /* 0x15c */ + u32 burstsize; /* 0x160: Master Interface Data Burst Size Register */ + u32 txttfilltuning; /* 0x164: Transmit FIFO Tuning Controls Register */ + u8 res6[24]; /* 0x168 */ + u32 configflag; /* 0x180: Configure Flag Register */ + u32 portsc1; /* 0x184: Port 1 Status and Control Register */ + u8 res7[28]; /* 0x188 */ + u32 otgsc; /* 0x1a4: On-The-Go Status and Control */ + u32 usbmode; /* 0x1a8: USB Mode Register */ + u32 endptsetupstat; /* 0x1ac: Endpoint Setup Status Register */ + u32 endpointprime; /* 0x1b0: Endpoint Initialization Register */ + u32 endptflush; /* 0x1b4: Endpoint Flush Register */ + u32 endptstatus; /* 0x1b8: Endpoint Status Register */ + u32 endptcomplete; /* 0x1bc: Endpoint Complete Register */ + u32 endptctrl[6]; /* 0x1c0: Endpoint Control Registers */ +}; + +/* ### define USB registers here + */ +#define USB_MAX_CTRL_PAYLOAD 64 +#define USB_DR_SYS_OFFSET 0x400 + +/* ep0 transfer state */ +#define WAIT_FOR_SETUP 0 +#define DATA_STATE_XMIT 1 +#define DATA_STATE_NEED_ZLP 2 +#define WAIT_FOR_OUT_STATUS 3 +#define DATA_STATE_RECV 4 + +/* Device Controller Capability Parameter register */ +#define DCCPARAMS_DC 0x00000080 +#define DCCPARAMS_DEN_MASK 0x0000001f + +/* Frame Index Register Bit Masks */ +#define USB_FRINDEX_MASKS 0x3fff +/* USB CMD Register Bit Masks */ +#define USB_CMD_RUN_STOP 0x00000001 +#define USB_CMD_CTRL_RESET 0x00000002 +#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010 +#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020 +#define USB_CMD_INT_AA_DOORBELL 0x00000040 +#define USB_CMD_ASP 0x00000300 +#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800 +#define USB_CMD_SUTW 0x00002000 +#define USB_CMD_ATDTW 0x00004000 +#define USB_CMD_ITC 0x00FF0000 + +/* bit 15,3,2 are frame list size */ +#define USB_CMD_FRAME_SIZE_1024 0x00000000 +#define USB_CMD_FRAME_SIZE_512 0x00000004 +#define USB_CMD_FRAME_SIZE_256 0x00000008 +#define USB_CMD_FRAME_SIZE_128 0x0000000C +#define USB_CMD_FRAME_SIZE_64 0x00008000 +#define USB_CMD_FRAME_SIZE_32 0x00008004 +#define USB_CMD_FRAME_SIZE_16 0x00008008 +#define USB_CMD_FRAME_SIZE_8 0x0000800C + +/* bit 9-8 are async schedule park mode count */ +#define USB_CMD_ASP_00 0x00000000 +#define USB_CMD_ASP_01 0x00000100 +#define USB_CMD_ASP_10 0x00000200 +#define USB_CMD_ASP_11 0x00000300 +#define USB_CMD_ASP_BIT_POS 8 + +/* bit 23-16 are interrupt threshold control */ +#define USB_CMD_ITC_NO_THRESHOLD 0x00000000 +#define USB_CMD_ITC_1_MICRO_FRM 0x00010000 +#define USB_CMD_ITC_2_MICRO_FRM 0x00020000 +#define USB_CMD_ITC_4_MICRO_FRM 0x00040000 +#define USB_CMD_ITC_8_MICRO_FRM 0x00080000 +#define USB_CMD_ITC_16_MICRO_FRM 0x00100000 +#define USB_CMD_ITC_32_MICRO_FRM 0x00200000 +#define USB_CMD_ITC_64_MICRO_FRM 0x00400000 +#define USB_CMD_ITC_BIT_POS 16 + +/* USB STS Register Bit Masks */ +#define USB_STS_INT 0x00000001 +#define USB_STS_ERR 0x00000002 +#define USB_STS_PORT_CHANGE 0x00000004 +#define USB_STS_FRM_LST_ROLL 0x00000008 +#define USB_STS_SYS_ERR 0x00000010 +#define USB_STS_IAA 0x00000020 +#define USB_STS_RESET 0x00000040 +#define USB_STS_SOF 0x00000080 +#define USB_STS_SUSPEND 0x00000100 +#define USB_STS_HC_HALTED 0x00001000 +#define USB_STS_RCL 0x00002000 +#define USB_STS_PERIODIC_SCHEDULE 0x00004000 +#define USB_STS_ASYNC_SCHEDULE 0x00008000 + +/* USB INTR Register Bit Masks */ +#define USB_INTR_INT_EN 0x00000001 +#define USB_INTR_ERR_INT_EN 0x00000002 +#define USB_INTR_PTC_DETECT_EN 0x00000004 +#define USB_INTR_FRM_LST_ROLL_EN 0x00000008 +#define USB_INTR_SYS_ERR_EN 0x00000010 +#define USB_INTR_ASYN_ADV_EN 0x00000020 +#define USB_INTR_RESET_EN 0x00000040 +#define USB_INTR_SOF_EN 0x00000080 +#define USB_INTR_DEVICE_SUSPEND 0x00000100 + +/* Device Address bit masks */ +#define USB_DEVICE_ADDRESS_MASK 0xFE000000 +#define USB_DEVICE_ADDRESS_BIT_POS 25 + +/* endpoint list address bit masks */ +#define USB_EP_LIST_ADDRESS_MASK 0xfffff800 + +/* PORTSCX Register Bit Masks */ +#define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001 +#define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002 +#define PORTSCX_PORT_ENABLE 0x00000004 +#define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008 +#define PORTSCX_OVER_CURRENT_ACT 0x00000010 +#define PORTSCX_OVER_CURRENT_CHG 0x00000020 +#define PORTSCX_PORT_FORCE_RESUME 0x00000040 +#define PORTSCX_PORT_SUSPEND 0x00000080 +#define PORTSCX_PORT_RESET 0x00000100 +#define PORTSCX_LINE_STATUS_BITS 0x00000C00 +#define PORTSCX_PORT_POWER 0x00001000 +#define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000 +#define PORTSCX_PORT_TEST_CTRL 0x000F0000 +#define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000 +#define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000 +#define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000 +#define PORTSCX_PHY_LOW_POWER_SPD 0x00800000 +#define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000 +#define PORTSCX_PORT_SPEED_MASK 0x0C000000 +#define PORTSCX_PORT_WIDTH 0x10000000 +#define PORTSCX_PHY_TYPE_SEL 0xC0000000 + +/* bit 11-10 are line status */ +#define PORTSCX_LINE_STATUS_SE0 0x00000000 +#define PORTSCX_LINE_STATUS_JSTATE 0x00000400 +#define PORTSCX_LINE_STATUS_KSTATE 0x00000800 +#define PORTSCX_LINE_STATUS_UNDEF 0x00000C00 +#define PORTSCX_LINE_STATUS_BIT_POS 10 + +/* bit 15-14 are port indicator control */ +#define PORTSCX_PIC_OFF 0x00000000 +#define PORTSCX_PIC_AMBER 0x00004000 +#define PORTSCX_PIC_GREEN 0x00008000 +#define PORTSCX_PIC_UNDEF 0x0000C000 +#define PORTSCX_PIC_BIT_POS 14 + +/* bit 19-16 are port test control */ +#define PORTSCX_PTC_DISABLE 0x00000000 +#define PORTSCX_PTC_JSTATE 0x00010000 +#define PORTSCX_PTC_KSTATE 0x00020000 +#define PORTSCX_PTC_SEQNAK 0x00030000 +#define PORTSCX_PTC_PACKET 0x00040000 +#define PORTSCX_PTC_FORCE_EN 0x00050000 +#define PORTSCX_PTC_BIT_POS 16 + +/* bit 27-26 are port speed */ +#define PORTSCX_PORT_SPEED_FULL 0x00000000 +#define PORTSCX_PORT_SPEED_LOW 0x04000000 +#define PORTSCX_PORT_SPEED_HIGH 0x08000000 +#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000 +#define PORTSCX_SPEED_BIT_POS 26 + +/* bit 28 is parallel transceiver width for UTMI interface */ +#define PORTSCX_PTW 0x10000000 +#define PORTSCX_PTW_8BIT 0x00000000 +#define PORTSCX_PTW_16BIT 0x10000000 + +/* bit 31-30 are port transceiver select */ +#define PORTSCX_PTS_UTMI 0x00000000 +#define PORTSCX_PTS_ULPI 0x80000000 +#define PORTSCX_PTS_FSLS 0xC0000000 +#define PORTSCX_PTS_BIT_POS 30 + +/* otgsc Register Bit Masks */ +#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001 +#define OTGSC_CTRL_VUSB_CHARGE 0x00000002 +#define OTGSC_CTRL_OTG_TERM 0x00000008 +#define OTGSC_CTRL_DATA_PULSING 0x00000010 +#define OTGSC_STS_USB_ID 0x00000100 +#define OTGSC_STS_A_VBUS_VALID 0x00000200 +#define OTGSC_STS_A_SESSION_VALID 0x00000400 +#define OTGSC_STS_B_SESSION_VALID 0x00000800 +#define OTGSC_STS_B_SESSION_END 0x00001000 +#define OTGSC_STS_1MS_TOGGLE 0x00002000 +#define OTGSC_STS_DATA_PULSING 0x00004000 +#define OTGSC_INTSTS_USB_ID 0x00010000 +#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000 +#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000 +#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000 +#define OTGSC_INTSTS_B_SESSION_END 0x00100000 +#define OTGSC_INTSTS_1MS 0x00200000 +#define OTGSC_INTSTS_DATA_PULSING 0x00400000 +#define OTGSC_INTR_USB_ID 0x01000000 +#define OTGSC_INTR_A_VBUS_VALID 0x02000000 +#define OTGSC_INTR_A_SESSION_VALID 0x04000000 +#define OTGSC_INTR_B_SESSION_VALID 0x08000000 +#define OTGSC_INTR_B_SESSION_END 0x10000000 +#define OTGSC_INTR_1MS_TIMER 0x20000000 +#define OTGSC_INTR_DATA_PULSING 0x40000000 + +/* USB MODE Register Bit Masks */ +#define USB_MODE_CTRL_MODE_IDLE 0x00000000 +#define USB_MODE_CTRL_MODE_DEVICE 0x00000002 +#define USB_MODE_CTRL_MODE_HOST 0x00000003 +#define USB_MODE_CTRL_MODE_RSV 0x00000001 +#define USB_MODE_CTRL_MODE_MASK 0x00000003 +#define USB_MODE_SETUP_LOCK_OFF 0x00000008 +#define USB_MODE_STREAM_DISABLE 0x00000010 +/* Endpoint Flush Register */ +#define EPFLUSH_TX_OFFSET 0x00010000 +#define EPFLUSH_RX_OFFSET 0x00000000 + +/* Endpoint Setup Status bit masks */ +#define EP_SETUP_STATUS_MASK 0x0000003F +#define EP_SETUP_STATUS_EP0 0x00000001 + +/* ENDPOINTCTRLx Register Bit Masks */ +#define EPCTRL_TX_ENABLE 0x00800000 +#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */ +#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */ +#define EPCTRL_TX_TYPE 0x000C0000 +#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */ +#define EPCTRL_TX_EP_STALL 0x00010000 +#define EPCTRL_RX_ENABLE 0x00000080 +#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */ +#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */ +#define EPCTRL_RX_TYPE 0x0000000C +#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */ +#define EPCTRL_RX_EP_STALL 0x00000001 + +/* bit 19-18 and 3-2 are endpoint type */ +#define EPCTRL_EP_TYPE_CONTROL 0 +#define EPCTRL_EP_TYPE_ISO 1 +#define EPCTRL_EP_TYPE_BULK 2 +#define EPCTRL_EP_TYPE_INTERRUPT 3 +#define EPCTRL_TX_EP_TYPE_SHIFT 18 +#define EPCTRL_RX_EP_TYPE_SHIFT 2 + +/* SNOOPn Register Bit Masks */ +#define SNOOP_ADDRESS_MASK 0xFFFFF000 +#define SNOOP_SIZE_ZERO 0x00 /* snooping disable */ +#define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */ +#define SNOOP_SIZE_8KB 0x0C +#define SNOOP_SIZE_16KB 0x0D +#define SNOOP_SIZE_32KB 0x0E +#define SNOOP_SIZE_64KB 0x0F +#define SNOOP_SIZE_128KB 0x10 +#define SNOOP_SIZE_256KB 0x11 +#define SNOOP_SIZE_512KB 0x12 +#define SNOOP_SIZE_1MB 0x13 +#define SNOOP_SIZE_2MB 0x14 +#define SNOOP_SIZE_4MB 0x15 +#define SNOOP_SIZE_8MB 0x16 +#define SNOOP_SIZE_16MB 0x17 +#define SNOOP_SIZE_32MB 0x18 +#define SNOOP_SIZE_64MB 0x19 +#define SNOOP_SIZE_128MB 0x1A +#define SNOOP_SIZE_256MB 0x1B +#define SNOOP_SIZE_512MB 0x1C +#define SNOOP_SIZE_1GB 0x1D +#define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */ + +/* pri_ctrl Register Bit Masks */ +#define PRI_CTRL_PRI_LVL1 0x0000000C +#define PRI_CTRL_PRI_LVL0 0x00000003 + +/* si_ctrl Register Bit Masks */ +#define SI_CTRL_ERR_DISABLE 0x00000010 +#define SI_CTRL_IDRC_DISABLE 0x00000008 +#define SI_CTRL_RD_SAFE_EN 0x00000004 +#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002 +#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001 + +/* control Register Bit Masks */ +#define USB_CTRL_IOENB 0x00000004 +#define USB_CTRL_ULPI_INT0EN 0x00000001 + +/* Endpoint Queue Head data struct + * Rem: all the variables of qh are LittleEndian Mode + * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr + */ +struct ep_queue_head { + u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len + and IOS(15) */ + u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */ + u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */ + u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15), + MultO(11-10), STS (7-0) */ + u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */ + u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */ + u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */ + u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */ + u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */ + u32 res1; + u8 setup_buffer[8]; /* Setup data 8 bytes */ + u32 res2[4]; +}; + +/* Endpoint Queue Head Bit Masks */ +#define EP_QUEUE_HEAD_MULT_POS 30 +#define EP_QUEUE_HEAD_ZLT_SEL 0x20000000 +#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16 +#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff) +#define EP_QUEUE_HEAD_IOS 0x00008000 +#define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001 +#define EP_QUEUE_HEAD_IOC 0x00008000 +#define EP_QUEUE_HEAD_MULTO 0x00000C00 +#define EP_QUEUE_HEAD_STATUS_HALT 0x00000040 +#define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080 +#define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF +#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0 +#define EP_QUEUE_FRINDEX_MASK 0x000007FF +#define EP_MAX_LENGTH_TRANSFER 0x4000 + +/* Endpoint Transfer Descriptor data struct */ +/* Rem: all the variables of td are LittleEndian Mode */ +struct ep_td_struct { + u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set + indicate invalid */ + u32 size_ioc_sts; /* Total bytes (30-16), IOC (15), + MultO(11-10), STS (7-0) */ + u32 buff_ptr0; /* Buffer pointer Page 0 */ + u32 buff_ptr1; /* Buffer pointer Page 1 */ + u32 buff_ptr2; /* Buffer pointer Page 2 */ + u32 buff_ptr3; /* Buffer pointer Page 3 */ + u32 buff_ptr4; /* Buffer pointer Page 4 */ + u32 res; + /* 32 bytes */ + dma_addr_t td_dma; /* dma address for this td */ + /* virtual address of next td specified in next_td_ptr */ + struct ep_td_struct *next_td_virt; +}; + +/* Endpoint Transfer Descriptor bit Masks */ +#define DTD_NEXT_TERMINATE 0x00000001 +#define DTD_IOC 0x00008000 +#define DTD_STATUS_ACTIVE 0x00000080 +#define DTD_STATUS_HALTED 0x00000040 +#define DTD_STATUS_DATA_BUFF_ERR 0x00000020 +#define DTD_STATUS_TRANSACTION_ERR 0x00000008 +#define DTD_RESERVED_FIELDS 0x80007300 +#define DTD_ADDR_MASK 0xFFFFFFE0 +#define DTD_PACKET_SIZE 0x7FFF0000 +#define DTD_LENGTH_BIT_POS 16 +#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \ + DTD_STATUS_DATA_BUFF_ERR | \ + DTD_STATUS_TRANSACTION_ERR) +/* Alignment requirements; must be a power of two */ +#define DTD_ALIGNMENT 0x20 +#define QH_ALIGNMENT 2048 + +/* Controller dma boundary */ +#define UDC_DMA_BOUNDARY 0x1000 + +int imx_barebox_load_usb(void __iomem *dr, void *dest); +int imx_barebox_start_usb(void __iomem *dr, void *dest); + +int imx6_barebox_load_usb(void *dest); +int imx6_barebox_start_usb(void *dest); + +int imx7_barebox_load_usb(void *dest); +int imx7_barebox_start_usb(void *dest); + +int imx8mm_barebox_load_usb(void *dest); +int imx8mm_barebox_start_usb(void *dest); + +static inline bool is_chipidea_udc_running(void __iomem *dr) +{ + struct usb_dr_device __iomem *dr_regs = dr; + + return (readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_DEVICE) + && (readl(&dr_regs->usbcmd) & USB_CMD_RUN_STOP); +} + +#endif /* __FSL_UDC_H */ diff --git a/include/soc/fsl/immap_lsch2.h b/include/soc/fsl/immap_lsch2.h index 4eb6658788..6a7dad3d5d 100644 --- a/include/soc/fsl/immap_lsch2.h +++ b/include/soc/fsl/immap_lsch2.h @@ -6,6 +6,9 @@ #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ #define __ARCH_FSL_LSCH2_IMMAP_H__ +#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) +#define SOC_MAJOR_VER_1_0 0x1 + #define gur_in32(a) in_be32(a) #define gur_out32(a, v) out_be32(a, v) @@ -56,6 +59,7 @@ #define LSCH2_PCIE1_ADDR (LSCH2_IMMR + 0x02400000) #define LSCH2_PCIE2_ADDR (LSCH2_IMMR + 0x02500000) #define LSCH2_PCIE3_ADDR (LSCH2_IMMR + 0x02600000) +#define LSCH2_SEC_ADDR (LSCH2_IMMR + 0x00700000) #define LSCH2_QDMA_BASE_ADDR (LSCH2_IMMR + 0x07380000) #define LSCH2_EHCI_USB1_ADDR (LSCH2_IMMR + 0x07600000) @@ -213,7 +217,67 @@ struct ccsr_gur { u32 dcfg_ccsr_reserved1; }; -#define SCFG_QSPI_CLKSEL 0x40100000 +/* LS102XA Device Configuration and Pin Control */ +struct ls102xa_ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_02c[0x70-0x2c]; + u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u8 res_084[0x94-0x84]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_09c[0xa4-0x9c]; + u32 svr; /* System version */ + u8 res_0a8[0xb0-0xa8]; + u32 rstcr; /* Reset control */ + u32 rstrqpblsr; /* Reset request preboot loader status */ + u8 res_0b8[0xc0-0xb8]; + u32 rstrqmr1; /* Reset request mask */ + u8 res_0c4[0xc8-0xc4]; + u32 rstrqsr1; /* Reset request status */ + u8 res_0cc[0xd4-0xcc]; + u32 rstrqwdtmrl; /* Reset request WDT mask */ + u8 res_0d8[0xdc-0xd8]; + u32 rstrqwdtsrl; /* Reset request WDT status */ + u8 res_0e0[0xe4-0xe0]; + u32 brrl; /* Boot release */ + u8 res_0e8[0x100-0xe8]; + u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 + u8 res_140[0x200-0x140]; + u32 scratchrw[4]; /* Scratch Read/Write */ + u8 res_210[0x300-0x210]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 crstsr; + u8 res_404[0x550-0x404]; + u32 sataliodnr; + u8 res_554[0x604-0x554]; + u32 pamubypenr; + u32 dmacr1; + u8 res_60c[0x740-0x60c]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[1]; /* Core Cluster n Topology Register */ + u8 res_848[0xe60-0x848]; + u32 ddrclkdr; + u8 res_e60[0xe68-0xe64]; + u32 ifcclkdr; + u8 res_e68[0xe80-0xe6c]; + u32 sdhcpcr; +}; + #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 @@ -237,15 +301,26 @@ struct ccsr_gur { #define SCFG_USB_PHY2 0x08500000 #define SCFG_USB_PHY3 0x08510000 #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c -#define USB_PHY_RX_EQ_VAL_1 0x0000 -#define USB_PHY_RX_EQ_VAL_2 0x0080 -#define USB_PHY_RX_EQ_VAL_3 0x0380 -#define USB_PHY_RX_EQ_VAL_4 0x0b80 + +#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 +#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 +#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 +#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 +#define SCFG_ENDIANCR_LE 0x80000000 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 +#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 +#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 +#define SCFG_SNPCNFGCR_EDMASNP 0x00020000 +#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 +#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 +#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 +#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 /* RGMIIPCR bit definitions*/ #define SCFG_RGMIIPCR_EN_AUTO BIT(3) @@ -352,4 +427,89 @@ struct ccsr_scfg { u32 pex3msir; }; -#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ +/* LS102XA Supplemental Configuration Unit */ +struct ls102xa_ccsr_scfg { + u32 dpslpcr; + u32 resv0[2]; + u32 etsecclkdpslpcr; + u32 resv1[5]; + u32 fuseovrdcr; + u32 pixclkcr; + u32 resv2[5]; + u32 spimsicr; + u32 resv3[6]; + u32 pex1pmwrcr; + u32 pex1pmrdsr; + u32 resv4[3]; + u32 usb3prm1cr; + u32 usb4prm2cr; + u32 pex1rdmsgpldlsbsr; + u32 pex1rdmsgpldmsbsr; + u32 pex2rdmsgpldlsbsr; + u32 pex2rdmsgpldmsbsr; + u32 pex1rdmmsgrqsr; + u32 pex2rdmmsgrqsr; + u32 spimsiclrcr; + u32 pexmscportsr[2]; + u32 pex2pmwrcr; + u32 resv5[24]; + u32 mac1_streamid; + u32 mac2_streamid; + u32 mac3_streamid; + u32 pex1_streamid; + u32 pex2_streamid; + u32 dma_streamid; + u32 sata_streamid; + u32 usb3_streamid; + u32 qe_streamid; + u32 sdhc_streamid; + u32 adma_streamid; + u32 letechsftrstcr; + u32 core0_sft_rst; + u32 core1_sft_rst; + u32 resv6[1]; + u32 usb_hi_addr; + u32 etsecclkadjcr; + u32 sai_clk; + u32 resv7[1]; + u32 dcu_streamid; + u32 usb2_streamid; + u32 ftm_reset; + u32 altcbar; + u32 qspi_cfg; + u32 pmcintecr; + u32 pmcintlecr; + u32 pmcintsr; + u32 qos1; + u32 qos2; + u32 qos3; + u32 cci_cfg; + u32 endiancr; + u32 etsecdmamcr; + u32 usb3prm3cr; + u32 resv9[1]; + u32 debug_streamid; + u32 resv10[5]; + u32 snpcnfgcr; + u32 hrstcr; + u32 intpcr; + u32 resv12[20]; + u32 scfgrevcr; + u32 coresrencr; + u32 pex2pmrdsr; + u32 eddrtqcfg; + u32 ddrc2cr; + u32 ddrc3cr; + u32 ddrc4cr; + u32 ddrgcr; + u32 resv13[120]; + u32 qeioclkcr; + u32 etsecmcr; + u32 sdhciovserlcr; + u32 resv14[61]; + u32 sparecr[8]; + u32 resv15[248]; + u32 core0sftrstsr; + u32 clusterpmcr; +}; +#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/include/soc/fsl/immap_lsch3.h b/include/soc/fsl/immap_lsch3.h new file mode 100644 index 0000000000..f25a6e46be --- /dev/null +++ b/include/soc/fsl/immap_lsch3.h @@ -0,0 +1,306 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * LayerScape Internal Memory Map + * + * Copyright 2017-2020 NXP + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __ARCH_FSL_LSCH3_IMMAP_H_ +#define __ARCH_FSL_LSCH3_IMMAP_H_ + +#define LSCH3_IMMR 0x01000000 + +// LSCH3_2: ls1028a, lx2162a, lx2160a +#define LSCH3_DDR_ADDR (LSCH3_IMMR + 0x00080000) +#define LSCH3_DDR2_ADDR (LSCH3_IMMR + 0x00090000) +#define LSCH3_DDR3_ADDR 0x08210000 +#define LSCH3_GUTS_ADDR (LSCH3_IMMR + 0x00E00000) +#define LSCH3_PMU_ADDR (LSCH3_IMMR + 0x00E30000) +#define LSCH3_RST_ADDR_LX21XXA (LSCH3_IMMR + 0x00e88180) +#define LSCH3_RST_ADDR (LSCH3_IMMR + 0x00E60000) +#define LSCH3_CH3_CLK_GRPA_ADDR (LSCH3_IMMR + 0x00300000) +#define LSCH3_CH3_CLK_GRPB_ADDR (LSCH3_IMMR + 0x00310000) +#define LSCH3_CH3_CLK_CTRL_ADDR (LSCH3_IMMR + 0x00370000) +#define LSCH3_QSPI_ADDR_LSCH3 (LSCH3_IMMR + 0x010c0000) +#define LSCH3_FSPI_ADDR (LSCH3_IMMR + 0x010c0000) +#define LSCH3_ESDHC1_BASE_ADDR (LSCH3_IMMR + 0x01140000) +#define LSCH3_ESDHC2_BASE_ADDR (LSCH3_IMMR + 0x01150000) +#define LSCH3_IFC_ADDR (LSCH3_IMMR + 0x01240000) +#define LSCH3_NS16550_COM1 (LSCH3_IMMR + 0x011C0500) +#define LSCH3_NS16550_COM2 (LSCH3_IMMR + 0x011C0600) +#define LSCH3_EDMA_ADDR (LSCH3_IMMR + 0x012c0000) +#define LSCH3_TIMER_ADDR (LSCH3_IMMR + 0x013e0000) +#define LSCH3_XHCI_USB1_ADDR (LSCH3_IMMR + 0x02100000) +#define LSCH3_XHCI_USB2_ADDR (LSCH3_IMMR + 0x02110000) +#define LSCH3_AHCI1_ADDR (LSCH3_IMMR + 0x02200000) +#define LSCH3_AHCI2_ADDR (LSCH3_IMMR + 0x02210000) +#define LSCH3_AHCI3_ADDR (LSCH3_IMMR + 0x02220000) +#define LSCH3_AHCI4_ADDR (LSCH3_IMMR + 0x02230000) +#define LSCH3_CCI400_ADDR (LSCH3_IMMR + 0x03090000) +#define LSCH3_SEC_ADDR (LSCH3_IMMR + 0x07000000) +#define LSCH3_SEC_JR0_ADDR (LSCH3_IMMR + 0x07010000) +#define LSCH3_SEC_JR1_ADDR (LSCH3_IMMR + 0x07020000) +#define LSCH3_SEC_JR2_ADDR (LSCH3_IMMR + 0x07030000) +#define LSCH3_SEC_JR3_ADDR (LSCH3_IMMR + 0x07040000) +#define LSCH3_QDMA_ADDR (LSCH3_IMMR + 0x07380000) +#define LSCH3_DISPLAY_ADDR (LSCH3_IMMR + 0x0e080000) +#define LSCH3_GPU_ADDR (LSCH3_IMMR + 0x0e0c0000) +#define LSCH3_PMU_CLTBENR (LSCH3_PMU_ADDR + 0x18A0) +#define LSCH3_PCTBENR_OFFSET (LSCH3_PMU_ADDR + 0x8A0) +#define LSCH3_SVR (LSCH3_GUTS_ADDR + 0xA4) + +#define LSCH3_WRIOP1_ADDR (LSCH3_IMMR + 0x7B80000) +#define LSCH3_WRIOP1_MDIO1 (LSCH3_WRIOP1_ADDR + 0x16000) +#define LSCH3_WRIOP1_MDIO2 (LSCH3_WRIOP1_ADDR + 0x17000) +#define LSCH3_SERDES_ADDR (LSCH3_IMMR + 0xEA0000) + +#define LSCH3_DCSR_DDR_ADDR 0x70012c000ULL +#define LSCH3_DCSR_DDR2_ADDR 0x70012d000ULL +#define LSCH3_DCSR_DDR3_ADDR 0x700132000ULL + +#define LSCH3_I2C1_BASE_ADDR (LSCH3_IMMR + 0x01000000) +#define LSCH3_I2C2_BASE_ADDR (LSCH3_IMMR + 0x01010000) +#define LSCH3_I2C3_BASE_ADDR (LSCH3_IMMR + 0x01020000) +#define LSCH3_I2C4_BASE_ADDR (LSCH3_IMMR + 0x01030000) +#define LSCH3_I2C5_BASE_ADDR (LSCH3_IMMR + 0x01040000) +#define LSCH3_I2C6_BASE_ADDR (LSCH3_IMMR + 0x01050000) +#define LSCH3_I2C7_BASE_ADDR (LSCH3_IMMR + 0x01060000) +#define LSCH3_I2C8_BASE_ADDR (LSCH3_IMMR + 0x01070000) + +/* EDMA */ +#define LSCH3_EDMA_BASE_ADDR (LSCH3_IMMR + 0x012c0000) + +/* MMU 500 */ +#define LSCH3_SMMU_SCR0 (SMMU_BASE + 0x0) +#define LSCH3_SMMU_SCR1 (SMMU_BASE + 0x4) +#define LSCH3_SMMU_SCR2 (SMMU_BASE + 0x8) +#define LSCH3_SMMU_SACR (SMMU_BASE + 0x10) +#define LSCH3_SMMU_IDR0 (SMMU_BASE + 0x20) +#define LSCH3_SMMU_IDR1 (SMMU_BASE + 0x24) + +#define LSCH3_SMMU_NSCR0 (SMMU_BASE + 0x400) +#define LSCH3_SMMU_NSCR2 (SMMU_BASE + 0x408) +#define LSCH3_SMMU_NSACR (SMMU_BASE + 0x410) + +/* Device Configuration */ +#define LSCH3_DCFG_BASE 0x01e00000 +#define LSCH3_DCFG_PORSR1 0x000 +#define LSCH3_DCFG_PORSR1_RCW_SRC 0xff800000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_SDHC1 0x04000000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_SDHC2 0x04800000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_I2C 0x05000000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_FSPI_NOR 0x07800000 +#define LSCH3_DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 +#define LSCH3_DCFG_RCWSR12 0x12c +#define LSCH3_DCFG_RCWSR12_SDHC_SHIFT 24 +#define LSCH3_DCFG_RCWSR12_SDHC_MASK 0x7 +#define LSCH3_DCFG_RCWSR13 0x130 +#define LSCH3_DCFG_RCWSR13_SDHC_SHIFT 3 +#define LSCH3_DCFG_RCWSR13_SDHC_MASK 0x7 +#define LSCH3_DCFG_RCWSR13_DSPI (0 << 8) +#define LSCH3_DCFG_RCWSR15 0x138 +#define LSCH3_DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 + +#define LSCH3_DCFG_DCSR_BASE 0X700100000ULL +#define LSCH3_DCFG_DCSR_PORCR1 0x000 + +/* Supplemental Configuration */ +#define LSCH3_SCFG_BASE 0x01fc0000 +#define LSCH3_SCFG_USB3PRM1CR 0x000 +#define LSCH3_SCFG_USB3PRM1CR_INIT 0x27672b2a +#define LSCH3_SCFG_USB_TXVREFTUNE 0x9 +#define LSCH3_SCFG_USB_SQRXTUNE_MASK 0x7 +#define LSCH3_SCFG_QSPICLKCTLR 0x10 + +#define LSCH3_DCSR_BASE 0x700000000ULL +#define LSCH3_DCSR_USB_PHY1 0x4600000 +#define LSCH3_DCSR_USB_PHY2 0x4610000 +#define LSCH3_DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C +#define LSCH3_DCSR_USB_IOCR1 0x108004 +#define LSCH3_DCSR_USB_PCSTXSWINGFULL 0x71 + +#ifndef __ASSEMBLY__ + +/* Global Utilities Block */ +struct lsch3_ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; /* General-purpose POR configuration 2 */ + u32 gpporcr3; + u32 gpporcr4; + u8 res_030[0x60-0x30]; + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_064[0x70-0x64]; + u32 devdisr; /* Device disable control 1 */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u8 res_088[0x94-0x88]; + u32 coredisr; /* Device disable control 7 */ + u8 res_098[0xa0-0x98]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u8 res_0a8[0x100-0xa8]; + u32 rcwsr[30]; /* Reset control word status */ + u8 res_178[0x200-0x178]; + u32 scratchrw[16]; /* Scratch Read/Write */ + u8 res_240[0x300-0x240]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 bootlocptrl; /* Boot location pointer low-order addr */ + u32 bootlocptrh; /* Boot location pointer high-order addr */ + u8 res_408[0x520-0x408]; + u32 usb1_amqr; + u32 usb2_amqr; + u8 res_528[0x530-0x528]; /* add more registers when needed */ + u32 sdmm1_amqr; + u32 sdmm2_amqr; + u8 res_538[0x550 - 0x538]; /* add more registers when needed */ + u32 sata1_amqr; + u32 sata2_amqr; + u32 sata3_amqr; + u32 sata4_amqr; + u8 res_560[0x570 - 0x560]; /* add more registers when needed */ + u32 misc1_amqr; + u8 res_574[0x590-0x574]; /* add more registers when needed */ + u32 spare1_amqr; + u32 spare2_amqr; + u32 spare3_amqr; + u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */ + u32 gencr[7]; /* General Control Registers */ + u8 res_63c[0x640-0x63c]; /* add more registers when needed */ + u32 cgensr1; /* Core General Status Register */ + u8 res_644[0x660-0x644]; /* add more registers when needed */ + u32 cgencr1; /* Core General Control Register */ + u8 res_664[0x740-0x664]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[4]; /* Core cluster n Topology Register */ + u8 res_864[0x920-0x864]; /* add more registers when needed */ + u32 ioqoscr[8]; /*I/O Quality of Services Register */ + u32 uccr; + u8 res_944[0x960-0x944]; /* add more registers when needed */ + u32 ftmcr; + u8 res_964[0x990-0x964]; /* add more registers when needed */ + u32 coredisablesr; + u8 res_994[0xa00-0x994]; /* add more registers when needed */ + u32 sdbgcr; /*Secure Debug Confifuration Register */ + u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */ + u32 ipbrr1; + u32 ipbrr2; + u8 res_858[0x1000-0xc00]; +}; + +struct rng4tst { + u32 rtmctl; /* misc. control register */ + u32 rtscmisc; /* statistical check misc. register */ + u32 rtpkrrng; /* poker range register */ + union { + u32 rtpkrmax; /* PRGM=1: poker max. limit register */ + u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ + }; + u32 rtsdctl; /* seed control register */ + union { + u32 rtsblim; /* PRGM=1: sparse bit limit register */ + u32 rttotsam; /* PRGM=0: total samples register */ + }; + u32 rtfreqmin; /* frequency count min. limit register */ + union { + u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ + u32 rtfreqcnt; /* PRGM=0: freq. count register */ + }; + u32 rsvd1[40]; + u32 rdsta; /*RNG DRNG Status Register*/ + u32 rsvd2[15]; +}; + +struct version_regs { + u32 crca; /* CRCA_VERSION */ + u32 afha; /* AFHA_VERSION */ + u32 kfha; /* KFHA_VERSION */ + u32 pkha; /* PKHA_VERSION */ + u32 aesa; /* AESA_VERSION */ + u32 mdha; /* MDHA_VERSION */ + u32 desa; /* DESA_VERSION */ + u32 snw8a; /* SNW8A_VERSION */ + u32 snw9a; /* SNW9A_VERSION */ + u32 zuce; /* ZUCE_VERSION */ + u32 zuca; /* ZUCA_VERSION */ + u32 ccha; /* CCHA_VERSION */ + u32 ptha; /* PTHA_VERSION */ + u32 rng; /* RNG_VERSION */ + u32 trng; /* TRNG_VERSION */ + u32 aaha; /* AAHA_VERSION */ + u32 rsvd[10]; + u32 sr; /* SR_VERSION */ + u32 dma; /* DMA_VERSION */ + u32 ai; /* AI_VERSION */ + u32 qi; /* QI_VERSION */ + u32 jr; /* JR_VERSION */ + u32 deco; /* DECO_VERSION */ +}; + +struct ccsr_sec { + u32 res0; + u32 mcfgr; /* Master CFG Register */ + u8 res1[0x4]; + u32 scfgr; + struct { + u32 ms; /* Job Ring LIODN Register, MS */ + u32 ls; /* Job Ring LIODN Register, LS */ + } jrliodnr[4]; + u8 res2[0x2c]; + u32 jrstartr; /* Job Ring Start Register */ + struct { + u32 ms; /* RTIC LIODN Register, MS */ + u32 ls; /* RTIC LIODN Register, LS */ + } rticliodnr[4]; + u8 res3[0x1c]; + u32 decorr; /* DECO Request Register */ + struct { + u32 ms; /* DECO LIODN Register, MS */ + u32 ls; /* DECO LIODN Register, LS */ + } decoliodnr[16]; + u32 dar; /* DECO Avail Register */ + u32 drr; /* DECO Reset Register */ + u8 res5[0x4d8]; + struct rng4tst rng; /* RNG Registers */ + u8 res6[0x780]; + struct version_regs vreg; /* version registers since era 10 */ + u8 res7[0xa0]; + u32 crnr_ms; /* CHA Revision Number Register, MS */ + u32 crnr_ls; /* CHA Revision Number Register, LS */ + u32 ctpr_ms; /* Compile Time Parameters Register, MS */ + u32 ctpr_ls; /* Compile Time Parameters Register, LS */ + u8 res8[0x10]; + u32 far_ms; /* Fault Address Register, MS */ + u32 far_ls; /* Fault Address Register, LS */ + u32 falr; /* Fault Address LIODN Register */ + u32 fadr; /* Fault Address Detail Register */ + u8 res9[0x4]; + u32 csta; /* CAAM Status Register */ + u32 smpart; /* Secure Memory Partition Parameters */ + u32 smvid; /* Secure Memory Version ID */ + u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ + u32 ccbvid; /* CHA Cluster Block Version ID Register */ + u32 chavid_ms; /* CHA Version ID Register, MS */ + u32 chavid_ls; /* CHA Version ID Register, LS */ + u32 chanum_ms; /* CHA Number Register, MS */ + u32 chanum_ls; /* CHA Number Register, LS */ + u32 secvid_ms; /* SEC Version ID Register, MS */ + u32 secvid_ls; /* SEC Version ID Register, LS */ + u8 res10[0x6f020]; + u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ + u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ + u8 res11[0x8ffd8]; +}; + +#endif /*__ASSEMBLY__ */ +#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/include/soc/fsl/scfg.h b/include/soc/fsl/scfg.h new file mode 100644 index 0000000000..bea184218e --- /dev/null +++ b/include/soc/fsl/scfg.h @@ -0,0 +1,19 @@ +#ifndef __SOC_FSL_SCFG_H +#define __SOC_FSL_SCFG_H + +#include <soc/fsl/scfg.h> +#include <linux/compiler.h> + +enum scfg_endianess { + SCFG_ENDIANESS_INVALID, + SCFG_ENDIANESS_LITTLE, + SCFG_ENDIANESS_BIG, +}; + +void scfg_clrsetbits32(void __iomem *addr, u32 clear, u32 set); +void scfg_clrbits32(void __iomem *addr, u32 clear); +void scfg_setbits32(void __iomem *addr, u32 set); +void scfg_out16(void __iomem *addr, u16 val); +void scfg_init(enum scfg_endianess endianess); + +#endif /* __SOC_FSL_SCFG_H */ |