1 files changed, 42 insertions, 97 deletions

diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h
index c81c4d82c5..5df07772b3 100644
--- a/include/soc/imx8m/ddr.h
+++ b/include/soc/imx8m/ddr.h
@@ -8,11 +8,10 @@
 
 #include <io.h>
 #include <asm/types.h>
+#include <mach/imx/imx8m-regs.h>
+#include <soc/imx/ddr.h>
 
-#define DDRC_DDR_SS_GPR0		0x3d000000
-#define DDRC_IPS_BASE_ADDR_0		0x3f400000
-#define IP2APB_DDRPHY_IPS_BASE_ADDR(X)	(0x3c000000 + (X * 0x2000000))
-#define DDRPHY_MEM(X)			(0x3c000000 + (X * 0x2000000) + 0x50000)
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X)	MX8M_DDRC_PHY_BASE_ADDR
 
 #define DDRC_MSTR(X)             (DDRC_IPS_BASE_ADDR(X) + 0x00)
 #define DDRC_STAT(X)             (DDRC_IPS_BASE_ADDR(X) + 0x04)
@@ -320,119 +319,65 @@
 #define DRC_PERF_MON_MRR14_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
 #define DRC_PERF_MON_MRR15_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
 
-#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000))
+#define DDRC_IPS_BASE_ADDR(X) MX8M_DDRC_IPS_BASE_ADDR(X)
 
-/* user data type */
-enum fw_type {
-	FW_1D_IMAGE,
-	FW_2D_IMAGE,
-};
+int imx8m_ddr_init(struct dram_controller *dram, struct dram_timing_info *dram_timing);
 
-enum dram_type {
-	DRAM_TYPE_LPDDR4,
-	DRAM_TYPE_DDR4,
-};
+extern struct dram_controller imx8m_dram_controller;
 
-struct dram_cfg_param {
-	unsigned int reg;
-	unsigned int val;
-};
-
-struct dram_fsp_msg {
-	unsigned int drate;
-	enum fw_type fw_type;
-	struct dram_cfg_param *fsp_cfg;
-	unsigned int fsp_cfg_num;
-};
-
-struct dram_timing_info {
-	enum dram_type dram_type;
-	/* umctl2 config */
-	struct dram_cfg_param *ddrc_cfg;
-	unsigned int ddrc_cfg_num;
-	/* ddrphy config */
-	struct dram_cfg_param *ddrphy_cfg;
-	unsigned int ddrphy_cfg_num;
-	/* ddr fsp train info */
-	struct dram_fsp_msg *fsp_msg;
-	unsigned int fsp_msg_num;
-	/* ddr phy trained CSR */
-	struct dram_cfg_param *ddrphy_trained_csr;
-	unsigned int ddrphy_trained_csr_num;
-	/* ddr phy PIE */
-	struct dram_cfg_param *ddrphy_pie;
-	unsigned int ddrphy_pie_num;
-	/* initialized drate table */
-	unsigned int fsp_table[4];
-};
-
-extern struct dram_timing_info dram_timing;
+static inline int imx8mm_ddr_init(struct dram_timing_info *dram_timing,
+				  enum dram_type dram_type)
+{
+	imx8m_dram_controller.ddrc_type = DDRC_TYPE_MM;
+	imx8m_dram_controller.dram_type = dram_type;
 
-enum ddrc_type {
-	DDRC_TYPE_MM,
-	DDRC_TYPE_MN,
-	DDRC_TYPE_MQ,
-	DDRC_TYPE_MP,
-};
+	ddr_get_firmware(dram_type);
 
-int imx8mm_ddr_init(struct dram_timing_info *timing_info);
-int imx8mn_ddr_init(struct dram_timing_info *timing_info);
-int imx8mq_ddr_init(struct dram_timing_info *timing_info);
-int imx8mp_ddr_init(struct dram_timing_info *timing_info);
-int ddr_cfg_phy(struct dram_timing_info *timing_info, enum ddrc_type type);
-void load_lpddr4_phy_pie(void);
-void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
-void dram_config_save(struct dram_timing_info *info, unsigned long base);
+	return imx8m_ddr_init(&imx8m_dram_controller, dram_timing);
+}
 
-/* utils function for ddr phy training */
-int wait_ddrphy_training_complete(void);
-void ddrphy_init_set_dfi_clk(unsigned int drate, enum ddrc_type type);
-void ddrphy_init_read_msg_block(enum fw_type type);
+static inline int imx8mn_ddr_init(struct dram_timing_info *dram_timing,
+				  enum dram_type dram_type)
+{
+	imx8m_dram_controller.ddrc_type = DDRC_TYPE_MN;
+	imx8m_dram_controller.dram_type = dram_type;
 
-void update_umctl2_rank_space_setting(unsigned int pstat_num,
-				      enum ddrc_type type);
-void get_trained_CDD(unsigned int fsp);
+	ddr_get_firmware(dram_type);
 
-#define reg32_write(a, v)	writel(v, a)
-#define reg32_read(a)		readl(a)
+	return imx8m_ddr_init(&imx8m_dram_controller, dram_timing);
+}
 
-static inline void reg32setbit(unsigned long addr, u32 bit)
+static inline int imx8mq_ddr_init(struct dram_timing_info *dram_timing,
+				  enum dram_type dram_type)
 {
-	setbits_le32(addr, (1 << bit));
-}
+	imx8m_dram_controller.ddrc_type = DDRC_TYPE_MQ;
+	imx8m_dram_controller.dram_type = dram_type;
 
-#define dwc_ddrphy_apb_wr(addr, data) \
-	reg32_write(IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)) + 4 * (addr), data)
-#define dwc_ddrphy_apb_rd(addr) \
-	reg32_read(IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)) + 4 * (addr))
+	ddr_get_firmware(dram_type);
 
-extern bool imx8m_ddr_old_spreadsheet;
-extern struct dram_cfg_param ddrphy_trained_csr[];
-extern uint32_t ddrphy_trained_csr_num;
+	return imx8m_ddr_init(&imx8m_dram_controller, dram_timing);
+}
 
-enum ddrc_phy_firmware_offset {
-	DDRC_PHY_IMEM = 0x00050000U,
-	DDRC_PHY_DMEM = 0x00054000U,
-};
+static inline int imx8mp_ddr_init(struct dram_timing_info *dram_timing,
+				  enum dram_type dram_type)
+{
+	imx8m_dram_controller.ddrc_type = DDRC_TYPE_MP;
+	imx8m_dram_controller.dram_type = dram_type;
 
-void ddr_load_train_code(enum dram_type dram_type, enum fw_type type);
+	ddr_get_firmware(dram_type);
 
-void ddrc_phy_load_firmware(void __iomem *,
-			    enum ddrc_phy_firmware_offset,
-			    const u16 *, size_t);
+	return imx8m_ddr_init(&imx8m_dram_controller, dram_timing);
+}
 
-static inline bool dram_is_lpddr4(enum dram_type type)
+static inline int imx8m_wait_ddrphy_training_complete(void)
 {
-	return IS_ENABLED(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) &&
-		type == DRAM_TYPE_LPDDR4;
+	return wait_ddrphy_training_complete(&imx8m_dram_controller);
 }
 
-static inline bool dram_is_ddr4(enum dram_type type)
+static inline void imx8m_ddr_load_train_code(enum dram_type dram_type,
+					     enum fw_type fw_type)
 {
-	return IS_ENABLED(CONFIG_FIRMWARE_IMX_DDR4_PMU_TRAIN) &&
-		type == DRAM_TYPE_DDR4;
+	ddr_load_train_code(&imx8m_dram_controller, dram_type, fw_type);
 }
 
-#define DDRC_PHY_REG(x)	((x) * 4)
-
 #endif