diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-generic/barebox.lds.h | 4 | ||||
| -rw-r--r-- | include/asm-generic/bitsperlong.h | 22 | ||||
| -rw-r--r-- | include/asm-generic/posix_types.h | 90 | ||||
| -rw-r--r-- | include/asm-generic/swab.h | 2 | ||||
| -rw-r--r-- | include/bootsource.h | 1 | ||||
| -rw-r--r-- | include/console.h | 8 | ||||
| -rw-r--r-- | include/crc.h | 2 | ||||
| -rw-r--r-- | include/dhcp.h | 25 | ||||
| -rw-r--r-- | include/digest.h | 10 | ||||
| -rw-r--r-- | include/fcntl.h | 3 | ||||
| -rw-r--r-- | include/init.h | 2 | ||||
| -rw-r--r-- | include/io.h | 8 | ||||
| -rw-r--r-- | include/linux/mod_devicetable.h | 7 | ||||
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 204 | ||||
| -rw-r--r-- | include/linux/phy.h | 1 | ||||
| -rw-r--r-- | include/linux/types.h | 8 | ||||
| -rw-r--r-- | include/platform_data/cadence_qspi.h | 9 | ||||
| -rw-r--r-- | include/serial/imx-uart.h | 128 | ||||
| -rw-r--r-- | include/watchdog.h | 17 |
19 files changed, 511 insertions, 40 deletions
diff --git a/include/asm-generic/barebox.lds.h b/include/asm-generic/barebox.lds.h index e359187d7f..254397ee97 100644 --- a/include/asm-generic/barebox.lds.h +++ b/include/asm-generic/barebox.lds.h @@ -34,7 +34,9 @@ KEEP(*(.initcall.9)) \ KEEP(*(.initcall.10)) \ KEEP(*(.initcall.11)) \ - KEEP(*(.initcall.12)) + KEEP(*(.initcall.12)) \ + KEEP(*(.initcall.13)) \ + KEEP(*(.initcall.14)) #define BAREBOX_CMDS KEEP(*(SORT_BY_NAME(.barebox_cmd*))) diff --git a/include/asm-generic/bitsperlong.h b/include/asm-generic/bitsperlong.h index 4ae54e07de..bb98650298 100644 --- a/include/asm-generic/bitsperlong.h +++ b/include/asm-generic/bitsperlong.h @@ -1,32 +1,10 @@ #ifndef __ASM_GENERIC_BITS_PER_LONG #define __ASM_GENERIC_BITS_PER_LONG -/* - * There seems to be no way of detecting this automatically from user - * space, so 64 bit architectures should override this in their - * bitsperlong.h. In particular, an architecture that supports - * both 32 and 64 bit user space must not rely on CONFIG_64BIT - * to decide it, but rather check a compiler provided macro. - */ -#ifndef __BITS_PER_LONG -#define __BITS_PER_LONG 32 -#endif - -#ifdef __KERNEL__ - #ifdef CONFIG_64BIT #define BITS_PER_LONG 64 #else #define BITS_PER_LONG 32 #endif /* CONFIG_64BIT */ -/* - * FIXME: The check currently breaks x86-64 build, so it's - * temporarily disabled. Please fix x86-64 and reenable - */ -#if 0 && BITS_PER_LONG != __BITS_PER_LONG -#error Inconsistent word size. Check asm/bitsperlong.h -#endif - -#endif /* __KERNEL__ */ #endif /* __ASM_GENERIC_BITS_PER_LONG */ diff --git a/include/asm-generic/posix_types.h b/include/asm-generic/posix_types.h new file mode 100644 index 0000000000..136f161e15 --- /dev/null +++ b/include/asm-generic/posix_types.h @@ -0,0 +1,90 @@ +#ifndef __ASM_GENERIC_POSIX_TYPES_H +#define __ASM_GENERIC_POSIX_TYPES_H + +#include <asm/bitsperlong.h> +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. + * + * First the types that are often defined in different ways across + * architectures, so that you can override them. + */ + +#ifndef __kernel_long_t +typedef long __kernel_long_t; +typedef unsigned long __kernel_ulong_t; +#endif + +#ifndef __kernel_ino_t +typedef __kernel_ulong_t __kernel_ino_t; +#endif + +#ifndef __kernel_mode_t +typedef unsigned int __kernel_mode_t; +#endif + +#ifndef __kernel_pid_t +typedef int __kernel_pid_t; +#endif + +#ifndef __kernel_ipc_pid_t +typedef int __kernel_ipc_pid_t; +#endif + +#ifndef __kernel_uid_t +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +#endif + +#ifndef __kernel_suseconds_t +typedef __kernel_long_t __kernel_suseconds_t; +#endif + +#ifndef __kernel_daddr_t +typedef int __kernel_daddr_t; +#endif + +#ifndef __kernel_uid32_t +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; +#endif + +#ifndef __kernel_old_uid_t +typedef __kernel_uid_t __kernel_old_uid_t; +typedef __kernel_gid_t __kernel_old_gid_t; +#endif + +#ifndef __kernel_old_dev_t +typedef unsigned int __kernel_old_dev_t; +#endif + +/* + * Most 32 bit architectures use "unsigned int" size_t, + * and all 64 bit architectures use "unsigned long" size_t. + */ +#ifndef __kernel_size_t +#if BITS_PER_LONG != 64 +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +#else +typedef __kernel_ulong_t __kernel_size_t; +typedef __kernel_long_t __kernel_ssize_t; +typedef __kernel_long_t __kernel_ptrdiff_t; +#endif +#endif + +/* + * anything below here should be completely generic + */ +typedef __kernel_long_t __kernel_off_t; +typedef long long __kernel_loff_t; +typedef __kernel_long_t __kernel_time_t; +typedef __kernel_long_t __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; + +#endif /* __ASM_GENERIC_POSIX_TYPES_H */ diff --git a/include/asm-generic/swab.h b/include/asm-generic/swab.h index a8e9029d9e..3ab5add54f 100644 --- a/include/asm-generic/swab.h +++ b/include/asm-generic/swab.h @@ -9,7 +9,7 @@ * valid if the compiler supports 64 bit data types. */ -#if __BITS_PER_LONG == 32 +#if BITS_PER_LONG == 32 #if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) #define __SWAB_64_THRU_32__ #endif diff --git a/include/bootsource.h b/include/bootsource.h index 4bca9b99ad..c6d3b3a98b 100644 --- a/include/bootsource.h +++ b/include/bootsource.h @@ -15,6 +15,7 @@ enum bootsource { BOOTSOURCE_ONENAND, BOOTSOURCE_HD, BOOTSOURCE_USB, + BOOTSOURCE_NET, }; #define BOOTSOURCE_INSTANCE_UNKNOWN -1 diff --git a/include/console.h b/include/console.h index 72b4a440e7..839ec17e50 100644 --- a/include/console.h +++ b/include/console.h @@ -52,8 +52,10 @@ struct console_device { struct list_head list; unsigned char f_active; + char active[4]; unsigned int baudrate; + unsigned int baudrate_param; const char *linux_console_name; }; @@ -62,6 +64,7 @@ int console_register(struct console_device *cdev); int console_unregister(struct console_device *cdev); struct console_device *console_get_by_dev(struct device_d *dev); +struct console_device *console_get_by_name(const char *name); extern struct list_head console_list; #define for_each_console(console) list_for_each_entry(console, &console_list, list) @@ -75,4 +78,9 @@ extern int barebox_loglevel; struct console_device *console_get_first_active(void); +int console_set_active(struct console_device *cdev, unsigned active); +unsigned console_get_active(struct console_device *cdev); +int console_set_baudrate(struct console_device *cdev, unsigned baudrate); +unsigned console_get_baudrate(struct console_device *cdev); + #endif diff --git a/include/crc.h b/include/crc.h index 10560c9fa9..4290f41c57 100644 --- a/include/crc.h +++ b/include/crc.h @@ -95,6 +95,6 @@ cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len); /* 16 bit CRC with polynomial x^16+x^12+x^5+1 */ -extern uint16_t cyg_crc16(unsigned char *s, int len); +extern uint16_t cyg_crc16(const unsigned char *s, int len); #endif /* _SERVICES_CRC_CRC_H_ */ diff --git a/include/dhcp.h b/include/dhcp.h new file mode 100644 index 0000000000..0796b30cf1 --- /dev/null +++ b/include/dhcp.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2015 PHYTEC Messtechnik GmbH, + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DHCP_H__ +#define __DHCP_H__ + +#define DHCP_DEFAULT_RETRY 20 + +struct dhcp_req_param { + char *hostname; + char *vendor_id; + char *client_id; + char *user_class; + char *client_uuid; +}; + +int dhcp(int retries, struct dhcp_req_param *param); + +#endif diff --git a/include/digest.h b/include/digest.h index 7f8d696eb6..7c6711b32a 100644 --- a/include/digest.h +++ b/include/digest.h @@ -68,14 +68,14 @@ void digest_free(struct digest *d); int digest_file_window(struct digest *d, const char *filename, unsigned char *hash, - unsigned char *sig, + const unsigned char *sig, ulong start, ulong size); int digest_file(struct digest *d, const char *filename, - unsigned char *hash, - unsigned char *sig); + unsigned char *hash, + const unsigned char *sig); int digest_file_by_name(const char *algo, const char *filename, - unsigned char *hash, - unsigned char *sig); + unsigned char *hash, + const unsigned char *sig); static inline int digest_init(struct digest *d) { diff --git a/include/fcntl.h b/include/fcntl.h index aed741e584..501b415035 100644 --- a/include/fcntl.h +++ b/include/fcntl.h @@ -17,11 +17,12 @@ #define O_NOFOLLOW 00400000 /* don't follow links */ /* barebox additional flags */ -#define O_RWSIZE_MASK 00000070 +#define O_RWSIZE_MASK 00000170 #define O_RWSIZE_SHIFT 3 #define O_RWSIZE_1 00000010 #define O_RWSIZE_2 00000020 #define O_RWSIZE_4 00000040 +#define O_RWSIZE_8 00000100 #define F_DUPFD 0 /* dup */ #define F_GETFD 1 /* get close_on_exec */ diff --git a/include/init.h b/include/init.h index 37c7eedf67..f619c951d3 100644 --- a/include/init.h +++ b/include/init.h @@ -39,6 +39,8 @@ typedef int (*initcall_t)(void); #define device_initcall(fn) __define_initcall("10",fn,10) #define crypto_initcall(fn) __define_initcall("11",fn,11) #define late_initcall(fn) __define_initcall("12",fn,12) +#define environment_initcall(fn) __define_initcall("13",fn,13) +#define postenvironment_initcall(fn) __define_initcall("14",fn,14) /* section for code used very early when * - we're not running from where we linked at diff --git a/include/io.h b/include/io.h index 8d885de68f..8eb56b061f 100644 --- a/include/io.h +++ b/include/io.h @@ -3,12 +3,4 @@ #include <asm/io.h> -/* cpu_read/cpu_write: cpu native io accessors */ -#define cpu_readb(a) __raw_readb(a) -#define cpu_readw(a) __raw_readw(a) -#define cpu_readl(a) __raw_readl(a) -#define cpu_writeb(v, a) __raw_writeb((v), (a)) -#define cpu_writew(v, a) __raw_writew((v), (a)) -#define cpu_writel(v, a) __raw_writel((v), (a)) - #endif /* __IO_H */ diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index c822075688..d8125214a0 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -17,4 +17,11 @@ struct pci_device_id { __u32 class, class_mask; /* (class,subclass,prog-if) triplet */ }; +#define SPI_NAME_SIZE 32 + +struct spi_device_id { + char name[SPI_NAME_SIZE]; + unsigned long driver_data; +}; + #endif /* LINUX_MOD_DEVICETABLE_H */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h new file mode 100644 index 0000000000..f099406c53 --- /dev/null +++ b/include/linux/mtd/spi-nor.h @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __LINUX_MTD_SPI_NOR_H +#define __LINUX_MTD_SPI_NOR_H + +/* + * Note on opcode nomenclature: some opcodes have a format like + * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number + * of I/O lines used for the opcode, address, and data (respectively). The + * FUNCTION has an optional suffix of '4', to represent an opcode which + * requires a 4-byte (32-bit) address. + */ + +/* Flash opcodes. */ +#define SPINOR_OP_WREN 0x06 /* Write enable */ +#define SPINOR_OP_RDSR 0x05 /* Read status register */ +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ +#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ +#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ +#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ +#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ +#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ +#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ +#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ +#define SPINOR_OP_RDCR 0x35 /* Read configuration register */ +#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ + +/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ +#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */ +#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */ +#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */ +#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ + +/* Used for SST flashes only. */ +#define SPINOR_OP_BP 0x02 /* Byte program */ +#define SPINOR_OP_WRDI 0x04 /* Write disable */ +#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ + +/* Used for Macronix and Winbond flashes. */ +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ + +/* Used for Spansion flashes only. */ +#define SPINOR_OP_BRWR 0x17 /* Bank register write */ + +/* Status Register bits. */ +#define SR_WIP 1 /* Write in progress */ +#define SR_WEL 2 /* Write enable latch */ +/* meaning of other SR_* bits may differ between vendors */ +#define SR_BP0 4 /* Block protect 0 */ +#define SR_BP1 8 /* Block protect 1 */ +#define SR_BP2 0x10 /* Block protect 2 */ +#define SR_SRWD 0x80 /* SR write protect */ + +#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */ + +/* Flag Status Register bits */ +#define FSR_READY 0x80 + +/* Configuration Register bits. */ +#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */ + +enum read_mode { + SPI_NOR_NORMAL = 0, + SPI_NOR_FAST, + SPI_NOR_DUAL, + SPI_NOR_QUAD, +}; + +/** + * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer + * @wren: command for "Write Enable", or 0x00 for not required + * @cmd: command for operation + * @cmd_pins: number of pins to send @cmd (1, 2, 4) + * @addr: address for operation + * @addr_pins: number of pins to send @addr (1, 2, 4) + * @addr_width: number of address bytes + * (3,4, or 0 for address not required) + * @mode: mode data + * @mode_pins: number of pins to send @mode (1, 2, 4) + * @mode_cycles: number of mode cycles (0 for mode not required) + * @dummy_cycles: number of dummy cycles (0 for dummy not required) + */ +struct spi_nor_xfer_cfg { + u8 wren; + u8 cmd; + u8 cmd_pins; + u32 addr; + u8 addr_pins; + u8 addr_width; + u8 mode; + u8 mode_pins; + u8 mode_cycles; + u8 dummy_cycles; +}; + +#define SPI_NOR_MAX_CMD_SIZE 8 +enum spi_nor_ops { + SPI_NOR_OPS_READ = 0, + SPI_NOR_OPS_WRITE, + SPI_NOR_OPS_ERASE, + SPI_NOR_OPS_LOCK, + SPI_NOR_OPS_UNLOCK, +}; + +enum spi_nor_option_flags { + SNOR_F_USE_FSR = BIT(0), +}; + +/** + * struct spi_nor - Structure for defining a the SPI NOR layer + * @mtd: point to a mtd_info structure + * @lock: the lock for the read/write/erase/lock/unlock operations + * @dev: point to a spi device, or a spi nor controller device. + * @page_size: the page size of the SPI NOR + * @addr_width: number of address bytes + * @erase_opcode: the opcode for erasing a sector + * @read_opcode: the read opcode + * @read_dummy: the dummy needed by the read operation + * @program_opcode: the program opcode + * @flash_read: the mode of the read + * @sst_write_second: used by the SST write operation + * @flags: flag options for the current SPI-NOR (SNOR_F_*) + * @cfg: used by the read_xfer/write_xfer + * @cmd_buf: used by the write_reg + * @prepare: [OPTIONAL] do some preparations for the + * read/write/erase/lock/unlock operations + * @unprepare: [OPTIONAL] do some post work after the + * read/write/erase/lock/unlock operations + * @read_xfer: [OPTIONAL] the read fundamental primitive + * @write_xfer: [OPTIONAL] the writefundamental primitive + * @read_reg: [DRIVER-SPECIFIC] read out the register + * @write_reg: [DRIVER-SPECIFIC] write data to the register + * @read: [DRIVER-SPECIFIC] read data from the SPI NOR + * @write: [DRIVER-SPECIFIC] write data to the SPI NOR + * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR + * at the offset @offs + * @priv: the private data + */ +struct spi_nor { + struct mtd_info *mtd; + struct mutex lock; + struct device_d *dev; + u32 page_size; + u8 addr_width; + u8 erase_opcode; + u8 read_opcode; + u8 read_dummy; + u8 program_opcode; + enum read_mode flash_read; + bool sst_write_second; + u32 flags; + struct spi_nor_xfer_cfg cfg; + u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; + + int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); + void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); + int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg, + u8 *buf, size_t len); + int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg, + u8 *buf, size_t len); + int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); + int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len, + int write_enable); + + int (*read)(struct spi_nor *nor, loff_t from, + size_t len, size_t *retlen, u_char *read_buf); + void (*write)(struct spi_nor *nor, loff_t to, + size_t len, size_t *retlen, const u_char *write_buf); + int (*erase)(struct spi_nor *nor, loff_t offs); + + void *priv; +}; + +/** + * spi_nor_scan() - scan the SPI NOR + * @nor: the spi_nor structure + * @name: the chip type name + * @mode: the read mode supported by the driver + * + * The drivers can use this fuction to scan the SPI NOR. + * In the scanning, it will try to get all the necessary information to + * fill the mtd_info{} and the spi_nor{}. + * + * The chip type name can be provided through the @name parameter. + * + * Return: 0 for success, others for failure. + */ +int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode); + +#endif diff --git a/include/linux/phy.h b/include/linux/phy.h index c0fd4ff19a..9a451a62d8 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -266,6 +266,7 @@ int phy_init(void); int phy_init_hw(struct phy_device *phydev); int phy_register_device(struct phy_device* dev); +void phy_unregister_device(struct phy_device *phydev); /** * phy_read - Convenience function for reading a given PHY register diff --git a/include/linux/types.h b/include/linux/types.h index c11e148c90..ce1a0ec84c 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -15,7 +15,6 @@ typedef __kernel_fd_set fd_set; typedef __kernel_dev_t dev_t; typedef __kernel_ino_t ino_t; typedef __kernel_mode_t mode_t; -typedef __kernel_nlink_t nlink_t; typedef __kernel_off_t off_t; typedef __kernel_pid_t pid_t; typedef __kernel_daddr_t daddr_t; @@ -158,6 +157,13 @@ typedef __u32 __bitwise __wsum; #define __aligned_be64 __be64 __attribute__((aligned(8))) #define __aligned_le64 __le64 __attribute__((aligned(8))) +/* A dma_addr_t can hold any valid DMA or bus address for the platform */ +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else +typedef u32 dma_addr_t; +#endif /* dma_addr_t */ + #ifdef CONFIG_PHYS_ADDR_T_64BIT typedef u64 phys_addr_t; typedef u64 phys_size_t; diff --git a/include/platform_data/cadence_qspi.h b/include/platform_data/cadence_qspi.h new file mode 100644 index 0000000000..4930edce50 --- /dev/null +++ b/include/platform_data/cadence_qspi.h @@ -0,0 +1,9 @@ +#ifndef __INCLUDE_PLATFORM_DATA_CADENCE_QSPI_H +#define __INCLUDE_PLATFORM_DATA_CADENCE_QSPI_H + +struct cadence_qspi_platform_data { + unsigned int ext_decoder; + unsigned int fifo_depth; +}; + +#endif /* __INCLUDE_PLATFORM_DATA_CADENCE_QSPI_H */ diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h new file mode 100644 index 0000000000..7275e6ac38 --- /dev/null +++ b/include/serial/imx-uart.h @@ -0,0 +1,128 @@ +#ifndef __IMX_UART_H__ +#define __IMX_UART_H__ + +#define URXD0 0x0 /* Receiver Register */ +#define URTX0 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz (i.MXL / i.MX1) */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz (i.MXL / i.MX1) */ +#define UCR3_RXDMUXSEL (1<<2) /* RXD Muxed input select (i.MX27) */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV6 (0b000<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV5 (0b001<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV4 (0b010<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV3 (0b011<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV2 (0b100<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV1 (0b101<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV7 (0b110<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +static inline int baudrate_to_ubir(int baudrate) +{ + return baudrate / 100 - 1; +} + +static inline int refclock_to_ubmr(int clock_hz) +{ + return clock_hz / 1600 - 1; +} + +#endif /* __IMX_UART_H__ */ diff --git a/include/watchdog.h b/include/watchdog.h index 3e2d08e876..7e37b7c22a 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -17,8 +17,25 @@ struct watchdog { int (*set_timeout)(struct watchdog *, unsigned); }; +#ifdef CONFIG_WATCHDOG int watchdog_register(struct watchdog *); int watchdog_deregister(struct watchdog *); int watchdog_set_timeout(unsigned); +#else +static inline int watchdog_register(struct watchdog *w) +{ + return 0; +} + +int watchdog_deregister(struct watchdog *w) +{ + return 0; +} + +int watchdog_set_timeout(unsigned t) +{ + return 0; +} +#endif #endif /* INCLUDE_WATCHDOG_H */ |