| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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<HACK>
For some yet unknown reason the processor on the i.MX35 3stack board (at
least on our board) has problem with an activated instruction cache and
booting from NAND: The copy-from-NFC-RAM-to-SDRAM routine doesn't loop.
It looks basically like this:
1:
ldmia
stmia
cmp
ble 1b
If the "cmp" instruction lives on address 0xbb000640 it doesn't work
with an activated i-cache. The processor flags are not properly updated.
So the ble won't jump back. This obviously break booting from nand.
This is why this patch disables the i-cache.
</HACK>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[mkl: split out custom display into separate patch]
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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ubifs from nand is default
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Export mc13892_reg_read, mc13892_reg_write and mc13892_set_bits
function instead of exposing the i2c interface.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Export mc9sdz60_reg_read, mc9sdz60_reg_write and mc9sdz60_set_bits
function instead of exposing the i2c interface.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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loop in i2c_imx_acked() in low bit rates it takes some time until the
ACK comes in.
Also add a delay before polling for bus not busy in i2c_imx_read.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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During i2c read the original pattern was:
1. write i2c slave address
2. wait for transmit complete + clear IIF
3. wait for receive acknowledge
4. wait for IIF interrupt
Due to the clear of the I2SR register, the IIF flag was cleared, too. So
in step 4 the Interrupt wasn't detected. To fix this problem, we move
the clean of IIF before the writing of the slave address. So that it
looks this way:
0. clear IIF
1. write i2c slave address
2. wait for transmit complete
3. wait for receive acknowledge
4. wait for IIF interrupt
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Currently all omap boards reside in boards/omap. This is
probably not a good idea as it leaves no good place to
put custom omap boards in. Anyway, make the boards compile
again until someone provides a better solution.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The RESET command was removed during the nand_imx.c driver rework.
The reset commant is necessary in order to get Micron Nand running
as they need a RESET command before being able to get any command.
Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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FMCR is (*((volatile u32 *)(x))) (0x10027814) and thus this leads
to a data abort.
Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The PLL initialisation does not work properly if run from
SDRAM. Move the initialisation code to lowlevel init which
is run in NFC RAM.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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- Add support for booting from NAND
- Add support for internal Boot mode
- Add I2C PMIC support
- Enable FEC Ethernet controller
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The flash header is used on different i.MXs other than the
i.MX25, so rename it. Also, add a possibility to put a flash
header on different offsets (0x100, 0x400 and 0x1000), needed
for different boot mediums.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Use the generic v1 driver instead
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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