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* Release v2013.05.1v2013.05.1Sascha Hauer2013-05-281-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* make: Add barebox_default_env.* to targetsSascha Hauer2013-05-271-0/+2
| | | | | | Otherwise it gets rebuilt everytime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: pbl: fix make dependenciesSascha Hauer2013-05-271-11/+2
| | | | | | | | The pbl used 'zbarebox.bin' as target instead of the real file. This lead to strange effects that the images depending on zbarebox.bin were only built every second time. This uses the full path as target. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pbl: Fix typo in make causing pbl files to be rebuiltSascha Hauer2013-05-271-1/+1
| | | | | | | We had pbl_cc__o_c instead of pbl_cc_o_c. This caused all pbl object files to be rebuilt everytime due to missing .cmd file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX53: tqma53: fix console entrySteffen Trumtrar2013-05-271-1/+1
| | | | | | | The default baseboard for the tqma53 (MBa53) uses UART2 for debug console. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: ccmx51: Another fix SDRAM size detectionAlexander Shiyan2013-05-231-2/+10
| | | | | | | | For CCMX51-boards now we do not use ESDCTL, but actual command for adding memory is missing. This patch fix this issue. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXS: fix SoC detectingJuergen Beisert2013-05-231-0/+1
| | | | | | | The missing 'break' statement lets look an i.MX23 like an i.MX28. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: ccxmx51: detect SDRAM size by board idSascha Hauer2013-05-233-21/+39
| | | | | | | | | | | | | | | | | | | | | | | | | This partly reverts: commit 697e02b74fddd80527e8ababba10239c83dba029 Author: Alexander Shiyan <shc_work@mail.ru> Date: Tue Jan 22 15:08:31 2013 +0400 ARM: ccmx51: Remove SDRAM size settings This patch removes SDRAM memory size setting from board due to auto detect last one by ESDCTL. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> The board originally configured the SDRAM controller for the maximum size and detected the usable SDRAM size by reading the board id. This became broken after switching to automatic SDRAM size detection by reading back ESDCTL values. This patch brings back the old behaviour. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: Allow disabling SDRAM autodetectionSascha Hauer2013-05-232-0/+15
| | | | | | | Some boards setup more memory than they actually have. The real memory size can then be detected later for example by reading a board id. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sama5d3xek: correct rootfs nand partitionAlexandre Belloni2013-05-231-1/+1
| | | | | Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: invalidate data caches during early initSascha Hauer2013-05-234-0/+30
| | | | | | | | | | Some SoCs come up with invalid entries in the data cache. This can lead to memory corruption when we enable them later, so invalidate the caches early. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de>
* ARM v7: added v7_mmu_cache_invalidate()Enrico Scholz2013-05-231-5/+19
| | | | | | | | | | | | | | | At least the iMX6 boot rom seems to jump into barebox with a non invalidated d-cache which causes data corruption when v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides stack or other valid data. That's why the cache must be invalided for this processors explicitly (e.g. in barebox_arm_reset_vector()). Operation differs from flush only in one instruction so that patch modifies the existing v7_mmu_cache_flush() function slightly by adding an optional argument. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM v7: v7_mmu_cache_flush(): do not restore r0-r3 (minor optimization)Enrico Scholz2013-05-231-2/+2
| | | | | | | | Registers 'r0' till 'r3' are scratch registers and do not need to be restored. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: properly init alignment trap bitLucas Stach2013-05-231-1/+1
| | | | | | | | | On ARMv7 the intention is to disable the alignment trap to be able to use hardware assisted unaligned load/stores. Fix the init to do the right thing. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM v7: fix mmu-off operationEnrico Scholz2013-05-231-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although conclusions in 50d1b2de8ea0f3b8d89fe3a97ce64315996ed4cb "ARM v7: Fix register corruption in v7_mmu_cache_off" are correct, the implemented fix is not complete because the following failure can happen: 1. d-cache contains the cache line around 'sp' 2. v7_mmu_cache_off() disables cache 3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack 4. v7_mmu_cache_flush() flushes d-cache and can override stack written by step 3. 5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which might be random data now. Patch avoids step 3 which is easy because 'lr' is never modified by the function. By using the 'r12' scratch register instead of 'r10', the whole initial 'push' can be avoided. Patch moves also the 'DMB' operation so that it is executed after data has been pushed on stack. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* fdt: Fix dt memreserve entrySascha Hauer2013-05-231-2/+1
| | | | | | | | The fdt reserve map needs address/size values, not address/end values like accidently done for generating the reserve entry for the dt. Reported-by: Jürgen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: fix the memset fixNicolas Pitre2013-05-231-20/+13
| | | | | | | | | | | | | | | | | | | | | | | | From Kernel commit 418df63a ARM: 7670/1: fix the memset fix | Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by | recent GCC (4.7.2) optimizations") attempted to fix a compliance issue | with the memset return value. However the memset itself became broken | by that patch for misaligned pointers. | | This fixes the above by branching over the entry code from the | misaligned fixup code to avoid reloading the original pointer. | | Also, because the function entry alignment is wrong in the Thumb mode | compilation, that fixup code is moved to the end. | | While at it, the entry instructions are slightly reworked to help dual | issue pipelines. | | Signed-off-by: Nicolas Pitre <nico@linaro.org> | Tested-by: Alexander Holler <holler@ahsoftware.de> | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* defaultenv-2: Fix settings entrySteffen Trumtrar2013-05-231-1/+1
| | | | | | | | There is no "settings-entries-edit" command. This results in a recursive call to the settings menu. Use the missing "boot-entries-edit" command instead. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Release v2013.05.0v2013.05.0Sascha Hauer2013-05-061-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clkdev: fix typoAntony Pavlov2013-05-061-1/+1
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* common/partition: check only for partition table typesHubert Feurstein2013-04-291-2/+2
| | | | | | | | The detection of the partition table fails when we have a barebox image in the MBR. So check only for partition table types. Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* common/filetype: move partition-table detection into own functionHubert Feurstein2013-04-292-12/+25
| | | | | Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXS/MCI: don't touch variables in the host structureJuergen Beisert2013-04-261-5/+5
| | | | | | | | | | MMC_BUS_WIDTH_* macros do not correspond with the real bus width. After setting a bus width larger than 1 bit the next call to change the frequency ends in the default handler and the host interface stays silently at the previous frequency. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: ccxmx51: Fix OTG Host USB modeAlexander Shiyan2013-04-261-1/+2
| | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: fix typosAntony Pavlov2013-04-262-3/+2
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: property: fix error messageSteffen Trumtrar2013-04-261-2/+2
| | | | | | | At least in standard oxford english one not is enough. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: fix how an initrd is passed to LinuxUwe Kleine-König2013-04-261-1/+5
| | | | | | | | | | | | Linux expects linux,initrd-end to contain the first unused address. As this doesn't match the end semantic used by barebox (i.e. end contains the last used address) adding one is necessary. Without this change Linux fails for me to correctly extract a gzipped cpio archive provided as initrd. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX28: make chip reset via reset pin work againMarc Kleine-Budde2013-04-241-1/+5
| | | | | | | | | | | | | | | | | Since commit: 2ccd451 ARM i.MX28: change default watchdog reset method the external reset via the reset pin is broken. That commit overwrites the HW_CLKCTRL_RESET register with only WDOG_POR_DISABLE set, which results in disabling the external reset. This patch uses read-modify-write to set the WDOG_POR_DISABLE, leaving the WDOG_POR_DISABLE untouched. Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXS/Chumby: fix MCI device registrationJuergen Beisert2013-04-241-1/+1
| | | | | | | | | | | Due to some changes in the framework a resource size of zero does not map anything at all and it does it silently. Defining the resource size for the MCI interface make it work again on the Chumby. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ubimkvol: Typo fixAlexander Shiyan2013-04-221-1/+1
| | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* defaultenv-2: Fix verbose bootingSascha Hauer2013-04-181-1/+1
| | | | | | | | During option parsing we use the variable BOOT_BOOTMOPTS, all other scripts use BOOT_BOOTM_OPTS though. Fix this by using the same variable everywhere. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtdraw: fix oob read and writeEric Bénard2013-04-121-0/+2
| | | | | | | | | | | | actually ops.ooboffs is not defaulted so when its value gets added to chip->oob_poi in nand_fill_oob or nand_transfer_oob the respective memcpy is using a wrong address. With this patch, both md -s /dev/nandraw0 and cp xyz /dev/nandraw0.sb are working fine on an i.MX28 target (instead of crashing the board). Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* dtc: remove autogenerated modules.orderSascha Hauer2013-04-111-0/+0
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: Fix bug if probe parameter is omittedAlexander Shiyan2013-04-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox@Phytec phyCORE-i.MX27:/ mci0.probe= unable to handle NULL pointer dereference at address 0x00000000 pc : [<a7f24700>] lr : [<a7f193f4>] sp : a7fff8e0 ip : 00000000 fp : 00000001 r10: 00000000 r9 : a6ffba8c r8 : 00000000 r7 : a7fffad0 r6 : a6ffbb04 r5 : a6fdd5cc r4 : a6fdd658 r3 : a7f18760 r2 : 00000000 r1 : 00000000 r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 [<a7f24700>] (simple_strtoul+0xc/0xc0) from [<a7f193f4>] (mci_set_probe+0xc94/0xd64) [<a7f193f4>] (mci_set_probe+0xc94/0xd64) from [<a7f252cc>] (dev_set_param+0x74/0x8c) [<a7f252cc>] (dev_set_param+0x74/0x8c) from [<a7f0606c>] (setenv+0x60/0xd8) [<a7f0606c>] (setenv+0x60/0xd8) from [<a7f00820>] (set_local_var.isra.3+0x5c/0x7c) [<a7f00820>] (set_local_var.isra.3+0x5c/0x7c) from [<a7f01a6c>] (run_list_real+0x494/0x934) [<a7f01a6c>] (run_list_real+0x494/0x934) from [<a7f01400>] (parse_stream_outer+0x198/0x270) [<a7f01400>] (parse_stream_outer+0x198/0x270) from [<a7f0209c>] (run_shell+0x3c/0x7c) [<a7f0209c>] (run_shell+0x3c/0x7c) from [<a7f05494>] (execute_command+0x38/0x78) [<a7f05494>] (execute_command+0x38/0x78) from [<a7f01db8>] (run_list_real+0x7e0/0x934) [<a7f01db8>] (run_list_real+0x7e0/0x934) from [<a7f019ec>] (run_list_real+0x414/0x934) [<a7f39578>] (unwind_backtrace+0x0/0xa8) from [<a7f24ed4>] (panic+0x28/0x3c) [<a7f24ed4>] (panic+0x28/0x3c) from [<a7f39a3c>] (do_exception+0x10/0x14) [<a7f39a3c>] (do_exception+0x10/0x14) from [<a7f39ac8>] (do_data_abort+0x2c/0x38) [<a7f39ac8>] (do_data_abort+0x2c/0x38) from [<a7f39788>] (data_abort+0x48/0x60) Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: tqma53: call SoC lowlevel function earlySascha Hauer2013-04-052-1/+2
| | | | | | | | | | | With CONFIG_MMU_EARLY enabled the board does not survive the call to imx53_init_lowlevel(). This should not happen, but the reasons are currently unknown. This works on other boards like the i.MX53 QSB. This patch moves the call to imx53_init_lowlevel to barebox_arm_reset_vector() which is executed with MMU disabled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX53: split lowlevel function into early/nonearly versionSascha Hauer2013-04-053-5/+10
| | | | | | | | | clock_notifier_call_chain() can't be called before init time. Protecting it with IS_ENABLED(__PBL__) is not enough. This patch splits out a new imx53_init_lowlevel_early which can be called before init time and does not have the call to clock_notifier_call_chain() in it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX53: Fix pll216 setupSascha Hauer2013-04-043-4/+3
| | | | | | | | The value for i.MX53 216MHz is actually 432MHz. Use the same value as for i.MX51 which really corresponds to 216MHz. These are the same PLL216 values as U-Boot uses. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* net: fec: probe phy_mode from devicetreeSascha Hauer2013-04-041-1/+26
| | | | | | This allows to parse the phy mode from the devicetree. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of/net: Add net related of helpersSascha Hauer2013-04-044-0/+112
| | | | | | | | of_get_phy_mode to parse the phy mode from the devicetree and of_get_mac_address to parse a MAC address from the devicetree. Directly taken from the Kernel. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynq'Sascha Hauer2013-04-0455-42/+1698
|\ | | | | | | | | Conflicts: arch/arm/Makefile
| * ARM: zedboard: add ethernet deviceSteffen Trumtrar2013-04-032-1/+23
| | | | | | | | | | | | | | The ZedBoard has a connection for the GEM0. Use it. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: add support for ethernetSteffen Trumtrar2013-04-035-1/+22
| | | | | | | | | | | | | | | | Add support for the ethernet device 0 on the Zynq7000 SoC. The GEM is compatible to/the same one as the macb on at91. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net: macb: turn off endian_swp_pkt_enSteffen Trumtrar2013-04-032-0/+3
| | | | | | | | | | | | | | | | | | | | The core has a bit for swapping packet data endianism. Reset default from Cadence is off. Xilinx however, that uses this core on the Zynq SoCs, opted for on. Turn it off for all devices. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * macb: rename platform dataJosh Cartwright2013-04-0326-41/+64
| | | | | | | | | | | | | | | | | | | | The macb/gem core is used by the Zynq SoC. In preparation of sharing the macb driver between at91 and Zynq, rename the platform data to 'struct macb_platform_data', and move the definition to a common location. Signed-off-by: Josh Cartwright <joshc@eso.teric.us> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: Add support for the Avnet ZedboardSteffen Trumtrar2013-03-277-0/+415
| | | | | | | | | | | | | | | | | | The Avnet ZedBoard is an evalboard with a Zynq-7020 based MPSoC. There is also a Digilent ZedBoard, that is the same but only for academic customers. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: add zynq fsbl checksum scriptSteffen Trumtrar2013-03-275-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | The bootrom only reads an image if the correct checksum is present in the header. The calculation is pretty simple: sum over all words from 0x20 to 0x44 Two of this words are the image length. That is why the checksum can not be calculated until barebox_image_size is known. The easiest solution is a program that has to be run after make. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: add clk support for zynq7000Steffen Trumtrar2013-03-272-0/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the clocktree on zynq7000 SoCs. The patch is based on clocks.c from the larger patch ARM: zynq: add suppport for Zynq 7000 SoC by Josh Cartwright. The driver in that patch is converted to a platform_driver and code to enable plls was added. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: Add new architecture zynqSteffen Trumtrar2013-03-2712-1/+340
| | | | | | | | | | | | | | | | | | Add basic support for the Xilinx Zynq-7000 EPP architecture. The Zynq-7000 is an embedded processing platform that combines a Cortex A9 dualcore MPSoC with an Artix-7 FPGA. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * serial: Add driver for Cadence UARTSteffen Trumtrar2013-03-273-0/+313
| | | | | | | | | | | | | | Support for Cadence UART core. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/relocate'Sascha Hauer2013-04-0424-58/+456
|\ \ | | | | | | | | | | | | Conflicts: arch/arm/lib/barebox.lds.S
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