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* Release v2013.06.0v2013.06.0Sascha Hauer2013-06-021-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Avoid build error on "config SPI" is yMasaki Muranaka2013-06-021-0/+4
| | | | | | | | In case he configures with make ARCH=x85 menuconfig, config SPI will be set to "y". And he will got an error on spi.h. Signed-off-by: Masaki Muranaka <monaka@monami-ya.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: pbl: Always call pbl makeSascha Hauer2013-05-301-1/+1
| | | | | | | We always must decend into the pbl build. Otherwise it doesn't get rebuilt if only sourcefiles from the pbl are changed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX53 vincell: Fix lowlevel startupSascha Hauer2013-05-301-2/+2
| | | | | | This is a i.MX53 board, not i.MX51. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX53: tqma53: fix console entrySteffen Trumtrar2013-05-271-1/+1
| | | | | | | The default baseboard for the tqma53 (MBa53) uses UART2 for debug console. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zynq: Add cmd to generate zynq imageSascha Hauer2013-05-251-2/+5
| | | | | | | | Add a command to generate the zynq image instead of generating it directly. This causes a rebuild exactly when necessary and prints a "ZYNQ-IMG" to the commandline during compilation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* make: Add barebox_default_env.* to targetsSascha Hauer2013-05-251-0/+2
| | | | | | Otherwise it gets rebuilt everytime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: pbl: fix make dependenciesSascha Hauer2013-05-251-11/+2
| | | | | | | | The pbl used 'zbarebox.bin' as target instead of the real file. This lead to strange effects that the images depending on zbarebox.bin were only built every second time. This uses the full path as target. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pbl: Fix typo in make causing pbl files to be rebuiltSascha Hauer2013-05-251-1/+1
| | | | | | | We had pbl_cc__o_c instead of pbl_cc_o_c. This caused all pbl object files to be rebuilt everytime due to missing .cmd file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: invalidate data caches during early initSascha Hauer2013-05-234-0/+30
| | | | | | | | | | Some SoCs come up with invalid entries in the data cache. This can lead to memory corruption when we enable them later, so invalidate the caches early. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de>
* ARM v7: added v7_mmu_cache_invalidate()Enrico Scholz2013-05-231-5/+19
| | | | | | | | | | | | | | | At least the iMX6 boot rom seems to jump into barebox with a non invalidated d-cache which causes data corruption when v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides stack or other valid data. That's why the cache must be invalided for this processors explicitly (e.g. in barebox_arm_reset_vector()). Operation differs from flush only in one instruction so that patch modifies the existing v7_mmu_cache_flush() function slightly by adding an optional argument. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM v7: v7_mmu_cache_flush(): do not restore r0-r3 (minor optimization)Enrico Scholz2013-05-231-2/+2
| | | | | | | | Registers 'r0' till 'r3' are scratch registers and do not need to be restored. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: properly init alignment trap bitLucas Stach2013-05-231-1/+1
| | | | | | | | | On ARMv7 the intention is to disable the alignment trap to be able to use hardware assisted unaligned load/stores. Fix the init to do the right thing. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* defaultenv-2: Fix settings entrySteffen Trumtrar2013-05-231-1/+1
| | | | | | | | There is no "settings-entries-edit" command. This results in a recursive call to the settings menu. Use the missing "boot-entries-edit" command instead. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: fix the memset fixNicolas Pitre2013-05-231-20/+13
| | | | | | | | | | | | | | | | | | | | | | | | From Kernel commit 418df63a ARM: 7670/1: fix the memset fix | Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by | recent GCC (4.7.2) optimizations") attempted to fix a compliance issue | with the memset return value. However the memset itself became broken | by that patch for misaligned pointers. | | This fixes the above by branching over the entry code from the | misaligned fixup code to avoid reloading the original pointer. | | Also, because the function entry alignment is wrong in the Thumb mode | compilation, that fixup code is moved to the end. | | While at it, the entry instructions are slightly reworked to help dual | issue pipelines. | | Signed-off-by: Nicolas Pitre <nico@linaro.org> | Tested-by: Alexander Holler <holler@ahsoftware.de> | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* fdt: Fix dt memreserve entrySascha Hauer2013-05-211-2/+1
| | | | | | | | The fdt reserve map needs address/size values, not address/end values like accidently done for generating the reserve entry for the dt. Reported-by: Jürgen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM v7: fix mmu-off operationEnrico Scholz2013-05-171-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although conclusions in 50d1b2de8ea0f3b8d89fe3a97ce64315996ed4cb "ARM v7: Fix register corruption in v7_mmu_cache_off" are correct, the implemented fix is not complete because the following failure can happen: 1. d-cache contains the cache line around 'sp' 2. v7_mmu_cache_off() disables cache 3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack 4. v7_mmu_cache_flush() flushes d-cache and can override stack written by step 3. 5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which might be random data now. Patch avoids step 3 which is easy because 'lr' is never modified by the function. By using the 'r12' scratch register instead of 'r10', the whole initial 'push' can be avoided. Patch moves also the 'DMB' operation so that it is executed after data has been pushed on stack. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nand_base: sync flash detection functions with linux 3.9's codeEric Bénard2013-05-172-120/+268
| | | | | | | | | this fix the problems introduced when detecting non ONFI flashes in commit 4c2bdc8728016b3412523e3264651651fe752860 "nand_base: detect more ONFI flash" Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'pu/dhcp'Sascha Hauer2013-05-171-5/+10
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| * net: dhcp: Fix tftp servername handlingSascha Hauer2013-05-141-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | When the dhcp code discovered the tftp-server-name option it immediately tries to resolve the name. This can't succeed since the we are somewhere in the dhcp processing and the nameserver may not even be known. Fix this by resolving the name when dhcp is completed. While at it, do this in a way that net_set_serverip is only called when resolv() returns something useful. Otherwise we may end up overwriting a previously configured serverip which came from the bootp bp_siaddr field. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net: dhcp: Fix return value on ctrl-cSascha Hauer2013-05-141-2/+4
| | | | | | | | | | | | | | the dhcp command will return with 0 when ctrl-c is pressed. Fix this to -EINTR instead. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: ccmx51: Another fix SDRAM size detectionAlexander Shiyan2013-05-151-2/+10
|/ | | | | | | | For CCMX51-boards now we do not use ESDCTL, but actual command for adding memory is missing. This patch fix this issue. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* gpio: fix typosAntony Pavlov2013-05-122-2/+1
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: remove unused clkdev.hAntony Pavlov2013-05-122-13/+0
| | | | | | | | | | | | | | | | See also: commit eb84709192f1b616cd141594c34ddbc072c8d6ec Author: Sascha Hauer <s.hauer@pengutronix.de> Date: Mon Mar 25 15:18:38 2013 +0100 clk: remove unused __clk_[get|put] This is some unused code resulting from copying stuff from the kernel. Remove it. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXS: fix SoC detectingJuergen Beisert2013-05-081-0/+1
| | | | | | | The missing 'break' statement lets look an i.MX23 like an i.MX28. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MCI/MXS: fix signed/unsigned mismatchJuergen Beisert2013-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the MXS MCI driver with an eight bit capable eMMC results into the 'devinfo' message the interface uses '0' bits for data transfer: barebox:/ devinfo mxs_mci0 resources: num : 0 start : 0x80034000 size : 0x00002000 driver: mxs_mci bus: platform Interface Min. bus clock: 1476 Hz Max. bus clock: 48000000 Hz Current bus clock: 24000000 Hz Bus width: 0 bit The eight bit interface width is stored internally as value '2'. And a two bit '2' ends up into 0xfffffffe when used as an array index. Using an unsigned field instead fixes this issue: barebox:/ devinfo mxs_mci0 resources: num : 0 start : 0x80034000 size : 0x00002000 driver: mxs_mci bus: platform Interface Min. bus clock: 1476 Hz Max. bus clock: 48000000 Hz Current bus clock: 24000000 Hz Bus width: 8 bit Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: ccxmx51: detect SDRAM size by board idSascha Hauer2013-05-083-21/+39
| | | | | | | | | | | | | | | | | | | | | | | | | This partly reverts: commit 697e02b74fddd80527e8ababba10239c83dba029 Author: Alexander Shiyan <shc_work@mail.ru> Date: Tue Jan 22 15:08:31 2013 +0400 ARM: ccmx51: Remove SDRAM size settings This patch removes SDRAM memory size setting from board due to auto detect last one by ESDCTL. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> The board originally configured the SDRAM controller for the maximum size and detected the usable SDRAM size by reading the board id. This became broken after switching to automatic SDRAM size detection by reading back ESDCTL values. This patch brings back the old behaviour. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: Allow disabling SDRAM autodetectionSascha Hauer2013-05-082-0/+15
| | | | | | | Some boards setup more memory than they actually have. The real memory size can then be detected later for example by reading a board id. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sama5d3xek: correct rootfs nand partitionAlexandre Belloni2013-05-081-1/+1
| | | | | Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* qt1070: drop non used bufJean-Christophe PLAGNIOL-VILLARD2013-05-081-1/+0
| | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* commands/mem.c: drop non used DEVMEMJean-Christophe PLAGNIOL-VILLARD2013-05-081-2/+0
| | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX31 pcm037: fix erroneous IOMUX GPR setup in pcm037_usb_init()Andreas Pretzsch2013-05-071-3/+3
| | | | | | | | | | | | | | | | | | | In commit ad09b59f8bb58c27e3872b41f41beb1b9eb1aeb1 "ARM i.MX31: give register base addresses a proper MX31_ prefix", the IOMUX GPR setup to enable USBH2 was replaced with an incorrect source register. Instead of reading the GPR register, USBOTG HWHOST is used as rmw source, which contains 0x10020001. Beside the intended GPR[11] setup ("Enable USBH2 signals on AudioPort 3 and AudioPort6"), this erroneously also sets GPR[28] enable USBOTG loopback GPR[17] override DSR_DCE1 with USBOTG_DATA4 GPR[0] select FIR DMA requests instead of UART2 DMA Beside breaking UART2, it probably also broke some UART1 and USB OTG setups. Fix this and replace the address with the appropriate defines. Signed-off-by: Andreas Pretzsch <apr@cn-eng.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX31: cleanup MX31_ prefix: fix leftover IOMUXC_BASE definesAndreas Pretzsch2013-05-071-3/+3
| | | | | | | | | | | The prefix/cleanup series ad09b59f8bb58c27e3872b41f41beb1b9eb1aeb1 a8c6359667704ffc3bd2249dd76f3fbbb2134b55 4c53af062b38f15f6bc40c586e5760e640f5b8b1 missed a few unprefixed IOMUXC_BASE define users. Fix these. Signed-off-by: Andreas Pretzsch <apr@cn-eng.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/tegra'Sascha Hauer2013-05-0627-162/+1394
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| * tegra: add GPIO controller driverLucas Stach2013-04-146-0/+241
| | | | | | | | | | | | | | | | Taken from the Linux kernel, simplified and reworked to match barebox. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add generic meminitLucas Stach2013-04-142-8/+9
| | | | | | | | | | | | | | | | | | ODMdata tells us how much RAM is installed, so no need to define this at the board level. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add generic debug UART supportLucas Stach2013-04-147-40/+125
| | | | | | | | | | | | | | | | | | | | ODMdata tells us which UART to use for debugging purposes. This is agreed upon in both the upstream Linux kernel and U-Boot, so do it the same way in barebox. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add common lowlevel startupLucas Stach2013-04-149-11/+577
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All Tegra20 boards have a common startup sequence. Also there is an agreement on how to find out about the installed amount of RAM and other information needed by early startup. So as there is really no need to do any lowlevel stuff per board, we can just do it at the ARCH level. This also enables the first stage loading of barebox by detecting the currently running CPU and booting the main CPU cluster if neccesary. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add T20 power management controller driverLucas Stach2013-04-145-40/+111
| | | | | | | | | | | | | | | | Currently only implements system wide reset functionality. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add T20 timer driverLucas Stach2013-04-145-57/+133
| | | | | | | | | | | | | | | | | | | | Replace the ad-hoc clocksource implementation with a proper driver for the Tegra 20 timer. This driver is able to do the required hardware initialisation itself. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add driver for the clock and reset moduleLucas Stach2013-04-146-0/+154
| | | | | | | | | | | | | | | | | | | | Only a basic set of clocks is supported. This is a temporary solution and will go away as soon as the port of the Tegra common clock code from the Linux kernel is ready to go. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: switch to DT onlyLucas Stach2013-04-144-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | We will follow the Linux kernel and go devicetree only for Tegra. This doesn't prevent specific code for certain boards, but always requires a valid DTB for all boards. Also regenerate the AC100 defconfig to reflect this change. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: move default textbaseLucas Stach2013-04-141-1/+1
| | | | | | | | | | | | | | | | | | All available opensource tools and published BCT configurations use 0x10800 as the default textbase on Tegra 20. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: introduce Tegra 20 SoC typeLucas Stach2013-04-141-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | Tegra isn't a single architecture, but a collection of more or less similar chip families. Introduce the same conf define as used in the Linux kernel to differentiate between those families. Currently we are only supporting the Tegra20 chip type. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: unify spelling in Kconfig with Linux kernelLucas Stach2013-04-141-1/+1
| | | | | | | | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: switch to proper CPU typeLucas Stach2013-04-141-1/+1
| | | | | | | | | | | | | | | | Tegras main CPUs are all ARMv7. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/remove-config-h'Sascha Hauer2013-05-0653-682/+12
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| * | Remove unused config.hAlexander Shiyan2013-04-0952-676/+0
| | | | | | | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | Makefile: Create empty <config.h> if this header file is not needed by boardAlexander Shiyan2013-04-091-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | Patch creates empty <config.h> if this header is not needed by board. This will allow to remove many empty config.h files from boards. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/param'Sascha Hauer2013-05-0631-529/+538
|\ \ \ | | | | | | | | | | | | | | | | Conflicts: drivers/mci/mci-core.c
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-23 10:37:01 +0000