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* Merge branch 'for-next/imx'Sascha Hauer2017-02-13116-265/+8713
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| * ARM: i.MX7: Add PSCI supportSascha Hauer2017-02-132-0/+90
| | | | | | | | | | | | | | This adds the SoC specific PSCI bits for i.MX7. Based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add PSCI supportSascha Hauer2017-02-1317-6/+1092
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains the barebox implementation for the ARM "Power State Coordination Interface" (PSCI). The interface is aimed at the generalization of code in the following power management scenarios: * Core idle management. * Dynamic addition and removal of cores, and secondary core boot. * big.LITTLE migration. * System shutdown and reset. In practice, all that's currently implemented is a way to enable the secondary core one some SoCs. With PSCI the Kernel is either started in nonsecure or in Hypervisor mode and PSCI is used to apply power to the secondary cores. The start mode is passed in the global.bootm.secure_state variable. This enum can contain "secure" (Kernel is started in secure mode, means no PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available) or "hyp" (Kernel is started in hyp mode, meaning it can support virtualization). We currently only support putting the secure monitor code into SDRAM, which means we always steal some amount of memory from the Kernel. To keep things simple for now we simply keep the whole barebox binary in memory The PSCI support has been tested on i.MX7 only so far. The only supported operations are CPU_ON and CPU_OFF. The PSCI and secure monitor code is based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add smc call supportSascha Hauer2017-02-083-0/+170
| | | | | | | | | | | | Taken from the Kernel: A wrapper to make a smc call from C. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add UNWIND macroSascha Hauer2017-02-081-0/+6
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: vf610: Add support for ZII VF610 Dev FamilyAndrey Smirnov2017-02-0718-0/+2853
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for ZII VF610 Dev based designs such as: - VF610 Dev, revision B - VF610 Dev, revision C - CFU1, revision A - SPU3, revision A - SCU4 AIB, revision C Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: Initialize CSUSascha Hauer2017-02-061-0/+14
| | | | | | | | | | | | | | The CSU needs to be initialized, otherwise we cannot access memory in non secure mode. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: Add imx7s.dtsiSascha Hauer2017-02-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | Needed for compiling the i.MX7 warp board which already includes this file. This file is necessary because the upstream dtsi file currently assigns MX7D_CLK_DUMMY to the gpt1 clock we use, so we won't get a meaningful clock rate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * pinctrl: i.MX7: Fix LPSR sel_imput settingSascha Hauer2017-02-062-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX7 has two pinmux controllers, the regular and the LPSR controller. The LPSR pinmux controller doesn't have any sel_input registers, instead they can be found in the regular pinmux controller. This means whenever we want to apply the the sel_input setting for the LPSR controller, we have to apply them to the regular controller instead. In barebox take the easy way out and just add the difference of the two base addresses to the register offset. The same issue is present in the Kernel aswell, but when the bootloader already configured the pins correctly nobody notices when the Kernel sel_input setup effectively is a no-op. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: i.MX7: setup ethernet clocksSascha Hauer2017-02-061-0/+11
| | | | | | | | | | | | | | Reparent ethernet clocks so that they can be used by the fec driver. The values are the same as U-Boot uses. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: i.MX7: do not register PLL bypass clocks as separate clocksSascha Hauer2017-02-061-119/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | In the Kernel the bypass bits in the PLLs are now registered as separate clocks and are no longer handled in the PLL code. In barebox we haven't made this step and there currently seems to be no reason to do so. This means that the bypass bits are currently modified in both the PLL driver and in the separate clocks which does not work properly. Drop all the bypass clocks to let the bypass bits be handled in the PLL driver exclusively. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: i.MX7: Fix ethernet clocksSascha Hauer2017-02-062-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | The original clock code from Linux registers some gates at base + 0x44e0, 0x44f0, 0x4500, 0x4510. These are not in the reference manual and do not seem to have any effect on the hardware. The reference manual lists clocks at 0x4700 and 0x4710 which Linux does not control at all. These clocks really do have an effect on the hardware and are needed for ethernet support. Register the existing clocks rather than the made up clocks to support ethernet. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: Add support for shared gatesSascha Hauer2017-02-063-1/+128
| | | | | | | | | | | | | | | | | | | | | | Sometimes a single software control knob controls multiple gates in hardware. This patch adds support for shared gates which help coping this situation. The first gate is registered with the hardware gate as usual, the others are registered as shared gates which does not have hardware control itself, but only switches the real hardware gate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: i.MX7: do clock reparenting when all clocks are initializedSascha Hauer2017-02-061-8/+23
| | | | | | | | | | | | | | | | | | By the time the i.MX7 clock driver probes the fixed clocks which are the roots of the clock tree are not yet present, so reparenting especially to one of the fixed clocks does not work. Move the tree setup to a later initcall when the fixed clocks are there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessarySascha Hauer2017-02-061-4/+4
| | | | | | | | | | | | CLK_OPS_PARENT_ENABLE was missing on some i.MX7 specific clocks. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: i.MX: clk-gate2: Allow to pass flagsSascha Hauer2017-02-062-9/+10
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: implement CLK_OPS_PARENT_ENABLESascha Hauer2017-02-062-4/+29
| | | | | | | | | | | | | | | | Some clocks may only be modified when their parent clocks are enabled. The kernel has the CLK_OPS_PARENT_ENABLE flag for this purpose. Implement it for barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: Keep enable count consistent over reparentSascha Hauer2017-02-061-6/+15
| | | | | | | | | | | | | | | | When reparenting a clock we have to make sure the new parent is enabled when the clock was enabled on the old parent. Also we have to decrease the old parents use counter when the clock was enabled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM i.MX: Add i.MX6SL supportAlexander Kurz2017-02-024-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Most i.MX6SL infrastructure is already covered in barebox by general i.MX6 support. Missing infrastructure provided in separate commits are * SoC type detection * Clock infrastructure Add the missing fsl,imx6sl-mmdc, so it will not be catched by fsl,imx6q-mmdc and the remaining bits and pieces to provide barebox i.MX6SL SoC support. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX6SL: import clock infrastructure from linuxAlexander Kurz2017-02-021-0/+329
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Import i.MX6SL clock infrastructure from linux clk-imx6sl.c To save space, clocks beeing unlikely usefull for bootloader purposes (SSI, SPDIF, EXTERN_AUDIO) were not imported. Further, the fixup code from linux mainline commits a49e6c4b8204 ("ARM: imx: add common clock support for fixup mux") cbe7fc8aaeef ("ARM: imx: add common clock support for fixup div") was ignored for this commit. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM i.MX: add SoC type detection for i.MX6SLAlexander Kurz2017-02-013-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX6 series SoC type is determined by barebox by examining the USB_ANALOG_DIGPROG aka IMX6_ANATOP_SI_REV register. This register is located at a common offset for all mx6 SoC - except for i.MX6SL where a different offset is used. This creates a dilemma while distinguishing the mx6sl from non-mx6sl SOC since the SoC type identification register location is type specific itself. Access to undocumented and probably invalid or unpredictable registers should be avoided as possible. For the mx6sl detection an access to the general USB_ANALOG_DIGPROG @0x260 cannot be avoided when running on mx6sl. This register contained the value 0x00014009 for different mx6sl Rev. 1.2 based e-book readers using MCIMX6L7DVN10AB and MCIMX6L8DVN10AB SoC. This implementation assumes the value of MAJOR_UPPER (here 0x01) to be smaller than the smallest non-6sl MAJOR_UPPER (0x61 for mx6s). Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM i.MX: move cpu_type macros in front of cpu_revision codeAlexander Kurz2017-02-011-20/+20
| | | | | | | | | | | | | | Preparational commit to enable the use of cpu_type macros in imx6_cpu_revision() Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: add AIPS base address definesAlexander Kurz2017-01-303-17/+112
| | | | | | | | | | | | | | Import the ARM IP bus base addresses from IMX7DRM 05/2016 AIPS Memory Map Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: Kconfig: ARCH_IMX7 selects COMMON_CLK_OF_PROVIDERAlexander Kurz2017-01-261-0/+2
| | | | | | | | | | | | | | Build of clk-imx7 depends on selection of COMMON_CLK_OF_PROVIDER Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM i.MX31 clk: add pll_ref_clk and MCU PLL bypass selectAlexander Kurz2017-01-261-5/+23
| | | | | | | | | | | | | | | | | | | | | | The three MX31 PLL may be clocked from either CKIH or a frequency-multiplied derivate of CKIL generated by the Frequency Pre Multiplier FPM. Add the pll_ref_clk selection infrastructure and support for MCU PLL bypass to support clock switching and boards not clocked CKIH. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * video: tc358767: add copyright linesAndrey Gusakov2017-01-201-0/+2
| | | | | | | | | | | | | | Add copyright lines for Zodiac who paid for driver development. Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: vf610-twr: remove unused variableSascha Hauer2017-01-201-1/+0
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * regulator: Add pfuze driverSascha Hauer2017-01-204-0/+180
| | | | | | | | | | | | | | | | This is not yet a regulator driver, only the register map is exported as /dev/pfuze* so the registers can be accessed for debugging purposes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: initialize architected timerSascha Hauer2017-01-201-0/+35
| | | | | | | | | | | | | | This is the same that U-Boot does. The registers are not documented. Without this the architected timer on the i.MX7 does not work. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX: Add WaRP7 board supportJuergen Borleis2017-01-2010-0/+294
| | | | | | | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * pinmmux: i.MX: add pin mux support for i.MX7Juergen Borleis2017-01-201-8/+32
| | | | | | | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX: Add i.MX7 base architecture supportJuergen Borleis2017-01-2015-0/+279
| | | | | | | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * watchdog: i.MX: Fix internal/external resetSascha Hauer2017-01-201-2/+14
| | | | | | | | | | | | | | | | | | | | | | The watchdog can either reset only the SoC or assert the WDOG_B output signal instead. On some boards it's necessary to use the external WDOG_B output to make sure that external devices like the PMIC are also properly resetted. This has been fixed in the Linux driver which honours a fsl,ext-reset-output device tree property to select between both ways. Do the same in the barebox driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * watchdog: i.MX: add soc_reset operationSascha Hauer2017-01-201-15/+25
| | | | | | | | | | | | | | | | On i.MX21 watchdog type the reset operation is really different from the watchdog enable/set timeout operation, so create an extra callback for this instead of folding both things together. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * serial: i.MX: add i.MX7 supportJuergen Borleis2017-01-191-0/+3
| | | | | | | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX: gpt: Add i.MX7 supportJuergen Borleis2017-01-191-0/+3
| | | | | | | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: i.MX7: Add missing USB clocksSascha Hauer2017-01-191-0/+3
| | | | | | | | | | | | The USB clocks are missing in the Kernel clock code. Add them here. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: i.MX: Add clock support for i.MX7Juergen Borleis2017-01-193-0/+908
| | | | | | | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: imx: Add clk-cpu supportSascha Hauer2017-01-193-0/+114
| | | | | | | | | | | | Taken from the kernel as of 4.10-rc3. Needed for i.MX7 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: i.MX: pllv3: Add support for the i.MX7 enet pllSascha Hauer2017-01-192-5/+19
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mci: imx-esdhci: remove wrong write protection testSascha Hauer2017-01-191-12/+2
| | | | | | | | | | | | | | | | | | | | | | Testing for the write protection bit to determine if a card is write protected or not is wrong. The bit may have the wrong value for permanently plugged cards (eMMC) or for boards using a GPIO for write protection detection. Since the core will test for write protection before actually calling into the driver this test can just be removed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mci: Allow to partition eMMC boot partitionsSascha Hauer2017-01-192-23/+56
| | | | | | | | | | | | | | | | | | So far the eMMC boot partitions cannot be partitioned from the device tree. Since they are often 4MiB in size they are big enough to hold a barebox image and the environment. Add partition parsing to the boot partitions to allow this usecase. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * of: partitions: force "partitions" subnodeSascha Hauer2017-01-191-6/+6
| | | | | | | | | | | | | | | | | | The binding states that a subnode containing partition subnodes should have the name "partitions". Enforce this so that we do not parse nodes with other names which may have partition descriptions for other disks. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * phy: usb-nop-xceiv: Add clock supportSascha Hauer2017-01-191-3/+15
| | | | | | | | | | | | | | As stated in the FIXME comment this is needed. Get and enable a "main_clk" just like the kernel does. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * usb: imx: Add clock supportSascha Hauer2017-01-191-0/+13
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * usb: imx: Add usbmisc support for i.MX7Sascha Hauer2017-01-191-0/+53
| | | | | | | | | | | | Taken directly from Linux-4.10-rc3 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * usb: imx: Make usb-misc multi instance safeSascha Hauer2017-01-193-17/+30
| | | | | | | | | | | | | | i.MX7 has two usbmisc devices, so we cannot use global instance variables anymore. Create a driver private data struct for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * serial: i.MX: Enable clockSascha Hauer2017-01-191-0/+1
| | | | | | | | | | | | For architectures which do not enable all clocks during initialization. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mci: imx-esdhc: Enable clockSascha Hauer2017-01-191-0/+1
| | | | | | | | | | | | For architectures which do not enable all clocks during initialization. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i2c: i.MX: Enable clockSascha Hauer2017-01-191-0/+1
| | | | | | | | | | | | For architectures which do not enable all clocks during initialization. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>