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* Release v2017.03.0v2017.03.0Sascha Hauer2017-03-101-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* usb: imx: Fix setting of dev->privSascha Hauer2017-03-091-1/+3
| | | | | | | | | Since fc10539f7d the usbmisc pointer must be stored in dev->priv, but dev->priv has never been set. Fix this. Fixes: fc10539f7d usb: imx: Make usb-misc multi instance safe Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* usb: imx: role_registered contains roleSascha Hauer2017-03-091-2/+2
| | | | | | | role_registered contains the role, it's not a bool indicating that a role is registered. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx233-olinuxino: add CONFIG_CONSOLE_ACTIVATE_ALLOleksij Rempel2017-03-091-0/+1
| | | | | | | | | if not set, barebox will use first console by default. On this board first console is KEYBOARD_GPIO, so we will end in unusable state. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* video: sdl fix typoJean-Christophe PLAGNIOL-VILLARD2017-03-061-1/+1
| | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* dma: apbh_dma: add missing array terminationSascha Hauer2017-03-061-1/+3
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: clk-imx6ul: Fixed conditional for enabling USB phy clocksRobin van der Gracht2017-03-031-1/+1
| | | | | Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: execute DMB before trying to flush cacheLucas Stach2017-03-031-0/+1
| | | | | | | | | | The CPU write buffer needs to be coherent with the cache, otherwise we might flush stale entries with the actual data stuck in the cache. This is really important on newer CPU core with bigger write buffers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: correctly identify ARMv6 K/ZLucas Stach2017-03-032-0/+16
| | | | | | | | | | The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other parts (including the cache handling) is still at v6. As we don't make use of the more advanced features of the v7 MMU in Barebox, it's okay to just override this to properly identify the CPU as ARMv6. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: align exception vectors to 32 byteLucas Stach2017-03-031-1/+1
| | | | | | | | | | | On ARMv7 the exception vectors inside the barebox binary are used directly by remapping the vectors base through the VBAR register. While VBAR allows to remap the exception vectors freely, it still imposes a minimum alignment of 32 byte, as the lower bits are treated as the exception vector offset. Enforce this alignment inside the barebox binary. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* scripts: mxsimage: Fix build with OpenSSL < 1.1.xSascha Hauer2017-03-021-31/+31
| | | | | | | Move the compatibility wrapper functions up so that they are defined before they are used. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nand-bb: fix writing to the end of a .bb deviceUwe Kleine-König2017-03-021-1/+1
| | | | | | | | As nand_bb_write_buf calls mtd_write(bb->mtd, cur_ofs, now, ...) the limit that now should be checked against is bb->mtd->size - cur_ofs. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* memcmp: fix comparison on short readUwe Kleine-König2017-03-021-2/+2
| | | | | | | | | | | | read() might return less than $count bytes which is only an upper limit. The user is supposed to repeat the command to fill a buffer completely. So use the convenience wrapper read_full in memcmp. This fixes memcmp on /dev/nand0 on an Armada XP. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* commands/mmc_extcsd: Relicense under GPLv2+Sascha Hauer2017-03-011-1/+1
| | | | | | | | GPLv3 is incompatible with the projects license. Relicense file under GPLv2+ Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Daniel Schultz <d.schultz@phytec.de>
* ARM: i.MX50: do not pass base address to imx53_boot_save_locAlexander Kurz2017-02-221-1/+1
| | | | | | | This is a follow-up on commit cf3dfafff4cb. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* i.MX: esdhc: fix imx-esdhc driver for non-OF boardsAlexander Kurz2017-02-141-15/+15
| | | | | | | | | | Commit 39f7a7ee8b68 ("i.MX: esdhc: Do not rely on CPU type for quirks") made imx-esdhc dependent on OF and broke probing for all non-OF boards. Since newer platforms like mx6 and vf610 are restricted to OF, the non-OF probing only needs to distinguish mx5 vs earlier SoC. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* i.MX: i2c: fix i2c-fsl for non-OF boardsAlexander Kurz2017-02-141-4/+10
| | | | | | | | | | With commit 4ed5b778a56b ("i.MX: i2c: Add Vybrid support") i2c-fsl probe returns -EINVAL for all non-OF boards. Since newer planforms, especially vf610 are restricted OF-only it is safe to assume "fsl,imx21-i2c" if CONFIG_OFDEVICE is not set. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/net'Sascha Hauer2017-02-132-41/+314
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| * net/phy: marvell: add support for 88e1510 to marvell phy driverUwe Kleine-König2017-01-131-3/+201
| | | | | | | | | | | | | | This is mostly copied verbatim from the Linux driver. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net/phy: marvell: improve config_aneg for 88E1121R and 88E1318SUwe Kleine-König2017-01-131-2/+76
| | | | | | | | | | | | | | This is taken from the Linux driver Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net/phy: marvell: align definition of MII_88E1121_PHY_MSCR to Linux driverUwe Kleine-König2017-01-131-3/+3
| | | | | | | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net/phy: marvell: change spacing to be more similar to the Linux driverUwe Kleine-König2017-01-131-28/+28
| | | | | | | | | | | | | | | | To make the barebox driver more similar to the Linux driver, only use a single space before the = in member initialisation. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net/phy: marvell: rename phy_driver array to match Linux driverUwe Kleine-König2017-01-131-2/+3
| | | | | | | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net/phy: marvell: 88E1540 LED registers already exist on 88E1121Uwe Kleine-König2017-01-131-5/+5
| | | | | | | | | | | | | | So rename accordingly to match the definition used by Linux Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net/phy: marvell: rename 88E1545 to 88E1540Uwe Kleine-König2017-01-132-3/+3
| | | | | | | | | | | | | | The Linux driver calls it 88E1540 so do it here, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mvebu'Sascha Hauer2017-02-132-3/+5
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| * | bus: mvebu-mbus: fixup correct device treeUwe Kleine-König2017-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When booting with an external device tree this external tree must be adapted, not the internal tree again. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | of: provide for_each_matching_node_fromUwe Kleine-König2017-01-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | This is for_each_matching_node for a given root similar to the other ..._from functions. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/misc'Sascha Hauer2017-02-135-6/+445
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| * | | spi: i.MX: Add driver for DSPIAndrey Smirnov2017-01-303-0/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for DSPI - SPI IP core found on various Freescale/NXP products (including Vybrid/VF610). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | usb: ehci: pass full speed devices to companion controllerPeter Mamonov2017-01-301-6/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the "Enhanced Host Controller Interface Specification for Universal Serial Bus" after a USB port reset the EHCI Driver checks the PortEnable bit in the PORTSC register. If set to a one, the connected device is a high-speed device [...]. At the time the EHCI Driver receives the port reset and enable request the LineStatus bits might indicate a low-speed device. Additionally, when the port reset process is complete, the PortEnable field may indicate that a full-speed device is attached. In either case the EHCI driver sets the PortOwner bit in the PORTSC register to a one to release port ownership to a companion host controller. Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | mtd: spi-nor: add support for s25fl208kPeter Mamonov2017-01-301-0/+1
| |/ / | | | | | | | | | | | | Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2017-02-13116-265/+8713
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| * | | ARM: i.MX7: Add PSCI supportSascha Hauer2017-02-132-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the SoC specific PSCI bits for i.MX7. Based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Add PSCI supportSascha Hauer2017-02-1317-6/+1092
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains the barebox implementation for the ARM "Power State Coordination Interface" (PSCI). The interface is aimed at the generalization of code in the following power management scenarios: * Core idle management. * Dynamic addition and removal of cores, and secondary core boot. * big.LITTLE migration. * System shutdown and reset. In practice, all that's currently implemented is a way to enable the secondary core one some SoCs. With PSCI the Kernel is either started in nonsecure or in Hypervisor mode and PSCI is used to apply power to the secondary cores. The start mode is passed in the global.bootm.secure_state variable. This enum can contain "secure" (Kernel is started in secure mode, means no PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available) or "hyp" (Kernel is started in hyp mode, meaning it can support virtualization). We currently only support putting the secure monitor code into SDRAM, which means we always steal some amount of memory from the Kernel. To keep things simple for now we simply keep the whole barebox binary in memory The PSCI support has been tested on i.MX7 only so far. The only supported operations are CPU_ON and CPU_OFF. The PSCI and secure monitor code is based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Add smc call supportSascha Hauer2017-02-083-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | Taken from the Kernel: A wrapper to make a smc call from C. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Add UNWIND macroSascha Hauer2017-02-081-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | i.MX: vf610: Add support for ZII VF610 Dev FamilyAndrey Smirnov2017-02-0718-0/+2853
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for ZII VF610 Dev based designs such as: - VF610 Dev, revision B - VF610 Dev, revision C - CFU1, revision A - SPU3, revision A - SCU4 AIB, revision C Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX7: Initialize CSUSascha Hauer2017-02-061-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The CSU needs to be initialized, otherwise we cannot access memory in non secure mode. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX7: Add imx7s.dtsiSascha Hauer2017-02-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed for compiling the i.MX7 warp board which already includes this file. This file is necessary because the upstream dtsi file currently assigns MX7D_CLK_DUMMY to the gpt1 clock we use, so we won't get a meaningful clock rate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | pinctrl: i.MX7: Fix LPSR sel_imput settingSascha Hauer2017-02-062-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX7 has two pinmux controllers, the regular and the LPSR controller. The LPSR pinmux controller doesn't have any sel_input registers, instead they can be found in the regular pinmux controller. This means whenever we want to apply the the sel_input setting for the LPSR controller, we have to apply them to the regular controller instead. In barebox take the easy way out and just add the difference of the two base addresses to the register offset. The same issue is present in the Kernel aswell, but when the bootloader already configured the pins correctly nobody notices when the Kernel sel_input setup effectively is a no-op. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: i.MX7: setup ethernet clocksSascha Hauer2017-02-061-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Reparent ethernet clocks so that they can be used by the fec driver. The values are the same as U-Boot uses. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: i.MX7: do not register PLL bypass clocks as separate clocksSascha Hauer2017-02-061-119/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Kernel the bypass bits in the PLLs are now registered as separate clocks and are no longer handled in the PLL code. In barebox we haven't made this step and there currently seems to be no reason to do so. This means that the bypass bits are currently modified in both the PLL driver and in the separate clocks which does not work properly. Drop all the bypass clocks to let the bypass bits be handled in the PLL driver exclusively. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: i.MX7: Fix ethernet clocksSascha Hauer2017-02-062-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original clock code from Linux registers some gates at base + 0x44e0, 0x44f0, 0x4500, 0x4510. These are not in the reference manual and do not seem to have any effect on the hardware. The reference manual lists clocks at 0x4700 and 0x4710 which Linux does not control at all. These clocks really do have an effect on the hardware and are needed for ethernet support. Register the existing clocks rather than the made up clocks to support ethernet. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: Add support for shared gatesSascha Hauer2017-02-063-1/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes a single software control knob controls multiple gates in hardware. This patch adds support for shared gates which help coping this situation. The first gate is registered with the hardware gate as usual, the others are registered as shared gates which does not have hardware control itself, but only switches the real hardware gate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: i.MX7: do clock reparenting when all clocks are initializedSascha Hauer2017-02-061-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By the time the i.MX7 clock driver probes the fixed clocks which are the roots of the clock tree are not yet present, so reparenting especially to one of the fixed clocks does not work. Move the tree setup to a later initcall when the fixed clocks are there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessarySascha Hauer2017-02-061-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | CLK_OPS_PARENT_ENABLE was missing on some i.MX7 specific clocks. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: i.MX: clk-gate2: Allow to pass flagsSascha Hauer2017-02-062-9/+10
| | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: implement CLK_OPS_PARENT_ENABLESascha Hauer2017-02-062-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some clocks may only be modified when their parent clocks are enabled. The kernel has the CLK_OPS_PARENT_ENABLE flag for this purpose. Implement it for barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: Keep enable count consistent over reparentSascha Hauer2017-02-061-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When reparenting a clock we have to make sure the new parent is enabled when the clock was enabled on the old parent. Also we have to decrease the old parents use counter when the clock was enabled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-25 12:44:55 +0000