| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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With serdev device support added there's now a corner case where:
1. There is a DT node for a serdev device on one of the UARTs
2. There is no driver that binds against serdev device's compatibility
string
with 1 and 2 being true it is possible to end up in a situation where
a particualr UART has not been initalized to any baudrate when
clock_notifier_call_chain() gets called. This effectively translates
to
set_baudrate(uart, 0);
which for LPUART driver result in a division by zero.
To avoid this problem, convert lpuart_serial_setbaudrate() to treat
zero baudrate as a request to disable the UART. While we are at it add
a BUG_ON() to lpuart_setbrg() to simplify finding any future bugs.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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compilation of fdtget was lost during the update to version 1.4.6.
We need this tool internally for the build process when imd support
is enabled.
Apparently our dtc code comes from the Kernel which doesn't have the
upstream version of fdtget.c and it doesn't compile. This patch
changes fdtget.c to the upstream version as of 1.4.6. This isn't
noticed in the Kernel because fdtget isn't compiled there.
Fixes: 8a8982541 scripts/dtc: Update to upstream version 1.4.6
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Not sure why it was working before, but with recent update of AArch64
GCC to 8.1.1 on my Fedora 28 machine, compiling barebox_arm_entry()
yields the following assembly:
0000000000002aac <barebox_arm_entry>:
2aac: a9bd7bfd stp x29, x30, [sp, #-48]!
2ab0: d1404023 sub x3, x1, #0x10, lsl #12
2ab4: d1004063 sub x3, x3, #0x10
2ab8: 910003fd mov x29, sp
2abc: 8b000063 add x3, x3, x0
2ac0: a90153f3 stp x19, x20, [sp, #16]
2ac4: aa0003f3 mov x19, x0
2ac8: aa0103f4 mov x20, x1
2acc: f90017e2 str x2, [sp, #40] <-- storing 'boarddata' on old stack
2ad0: 9100007f mov sp, x3 <-- setting up new stack
2ad4: 97ffffdd bl 2a48 <arm_early_mmu_cache_invalidate>
2ad8: f94017e2 ldr x2, [sp, #40] <--- sadness
2adc: aa1403e1 mov x1, x20
2ae0: aa1303e0 mov x0, x19
2ae4: 940000a1 bl 2d68 <barebox_multi_pbl_start>
Which result in AArch64 image (i.MX8MQ) not being bootable. With SP
marked as clobbered, the above assembly changes to the following:
0000000000002aac <barebox_arm_entry>:
2aac: a9bd7bfd stp x29, x30, [sp, #-48]!
2ab0: d1404023 sub x3, x1, #0x10, lsl #12
2ab4: d1004063 sub x3, x3, #0x10
2ab8: 910003fd mov x29, sp
2abc: a90153f3 stp x19, x20, [sp, #16]
2ac0: 8b000063 add x3, x3, x0
2ac4: aa0003f3 mov x19, x0
2ac8: aa0103f4 mov x20, x1
2acc: f90017a2 str x2, [x29, #40]
2ad0: 9100007f mov sp, x3
2ad4: 97ffffdd bl 2a48 <arm_early_mmu_cache_invalidate>
2ad8: f94017a2 ldr x2, [x29, #40]
2adc: aa1403e1 mov x1, x20
2ae0: aa1303e0 mov x0, x19
2ae4: 940000a1 bl 2d68 <barebox_multi_pbl_start>
now x29 is used to access stored x2 which avoids the problem and
allows the system to boot correctly.
The change is a no-op on AArch32.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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IS_ENABLED has to be passed the full symbol name including the CONFIG_
prefix. Otherwise IS_ENABLED evaluates to 0.
Fixes: 2877e08f9e1a ("ARM: phytec-som-am335x: Add autoenable")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
--
Cc: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When sparse support was (intended to be) made optional it was
effectively unconditionally disabled because
IS_ENABLED(USB_GADGET_FASTBOOT_SPARSE)
always evaluates to 0. To actually make use of the introduced kconfig
symbol the CONFIG_ prefix must not be skipped.
Fixes: f4b5d3eeb607 ("usb: gadget: fastboot: Make sparse support optional")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Gavin Schenk <g.schenk@eckelmann.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Make a static inline wrapper actually static inline.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When replacing a section with a PTE, we must make sure that the newly
initialized PTE entries are flushed from the cache before changing the
entry in the TTB. Otherwise a L1 TLB miss causes the hardware pagetable
walker to walk into a PTE with undefined content, causing exactly that
behaviour.
Move all the necessary cache flushing to arm_create_pte(), to avoid any
caller getting this wrong in the future.
Fixes: e3e54c644180 (ARM: mmu: Implement on-demand PTE allocation)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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A NO_PAD_CTRL flag used to keep a pad configuration untouched.
With commit 094820a63bfd ("i.MX: iomuxv3: Use helper functions in iomux-v3.h")
the NO_PAD_CTRL semantic changed to set a pad configurations to zero, which
breaks non-DT boards, where NO_PAD_CTRL is freqently used to keep a boot-up
default pad configuration, which often is non zero.
Restore the old semantic, dont write PAD_CTRL when NO_PAD_CTRL is set.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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OpenSSL 1.1.x made some of the types opaque, so peeking inside directly
doesn't work anymore. Use the correct accessors instead.
I've dropped the algorithm check, as EVP_PKEY_get0_RSA() already verifies
that the pubkey is RSA and returns NULL if it isn't.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fixes: e3e54c6441 ARM: mmu: Implement on-demand PTE allocation
PGD_FLAGS_WC_V7 lacks the PMD_TYPE_SECT and PMD_SECT_BUFFERABLE flags.
Without them a dma_alloc_writecombine() creates an invalid section when
it crosses a section boundary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
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Currently when cmdlinepart_do_parse() is called with an empty
partitions string then an unnamed partition with size 0 is created.
This is wrong of course and instead no partition should be
created.
With this barebox no longer crashes while booting when all partitions
are deleted on the commandline using "nand0.partitions="
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Read leveling delays are being specified as zero, so they are as good
as disabled and can be safely dropped.
Gate training delay is specified as 4/128 tCK for both data
slices. This setting, when applied to Data Byte 1, makes that slice
unusable* during POR startup which is somehow is mitigated by
double-reset hack in DCD.
Dropping gate training delays allows both VF610 Tower board and ZII
VF610 Dev board to sucessfully PoR-boot without the need for double
resetting of the DDRMC.
* The board fails to boot. When examined via JTAG in such a state
only even bytes of DDR memory are functional.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There's no point enabling write leveling DQS adjustement, while
setting offsets for both slices to zero. This code is effectively a
no-op, so drop it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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All of those registers contain paramters applicable only to write
leveling, gate training and read leveling procedures. They should have
no effect on normal mode of operations, so remove them from the common
settings file.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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CR151 contains parameters specific to HW gate training and read
leveling which are not an officially supported featre of the HW.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The only differential signals coming out of DDRMC to the memory chip
are CLK, DQS0 and DQS1. There rest of the pins are not, so there
should be no reason to configure them as such.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Although upstream U-Boot does not initialize this register in
vf610-twr code (it does so in code for Phytec's PCM052) multiple
revisions of VFxxx Controller Reference Manual state:
5.2.6.1 DUMMY PADS (DDR/QuadSPI)
There are two dummy pads that are useful for timing calibration of
DDR. These pads are internal only, but there corresponding IOMUX
register need to be programmed for correct operation of DDR. These
registers are:
* IOMUXC_DUMMY_DDRBYTE1 (0x400482DC)
* IOMUXC_DUMMY_DDRBYTE2 (0x400482E0)
DDR: Dummy pads for DDR must be configured before any DDR I/O
transactions are done. These pads simulate the input delay of the
I/O buffers from the DRAM devices and DDR configures the delays
accordingly.
Although current DCD works as is, add writes for those registers for
the sake of completness.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Both zii-vf610-dev and vf610-twr boards have same DDR layout. Since
provenance of those custom settings is unclear, drop them in favor of
what vf610-twr board does.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Some of the settings for VFxxx boards appear to be in violation of the
parameters specified by DDR chip's datasheet, so fix the code to
reconcile the differences. The changes are:
In vf610-ddr-cr-default.imxcfg:
- CR31: t_XSDLL is 468, should be 512
- CR161 t_ODTH8 (R & W) is 2, should be 6
In flash-header-zii-vf610-dev.imxcfg:
- CR12: WRLAT is 5, CL is 3,should be 5 and 6
- CR13: t_RC is 6, should be 21
- CR14: use default, more conservative t_FAW of 20
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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U-Boot was originally used as a source of DCD for VFxxx, so update our
settings against latest upstream (sha1:
b8aa55cb6414e512cce30bb7db3268eea934466d) to reconcile the
differences.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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A number of VFxxx boards copy DDR layout/design of vf610-twr board and
they all share DDR settings. Move those settings to a common file to
avoid code duplication.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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VFxxx support code in Barebox is written assuming a particular clock
setup in mind and all of the supported boards use it. Move the DCD
code responsible for that setup to a shared file to avoid code
duplication.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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A number of VFxxx boards copy DDR layout/design of vf610-twr board and
they all share DDR PHY settings. Move those settings to a common file
to avoid code duplication.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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A number of VFxxx boards copy DDR layout/design of vf610-twr board and
they all share IOMUX settings. Move those settings to a common file
to avoid code duplication.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Remove various bits of debug code, commented DCD commands and
separators as a small clean-up in preparation for commits that would
follow.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This is a port of Linux kernel commit
| commit 740129b36faf049e6845819144542a0455e1e285
| Author: Antony Pavlov <antonynpavlov@gmail.com>
| Date: Wed Apr 11 08:50:19 2018 +0100
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| MIPS: Use generic GCC library routines from lib/
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This commit is based on these linux kernel commits:
| commit b35cd9884fa5d81c9d5e7f57c9d03264ae2bd835
| Author: Palmer Dabbelt <palmer@dabbelt.com>
| Date: Tue May 23 10:28:26 2017 -0700
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| lib: Add shared copies of some GCC library routines
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| commit e3d5980568fdf83c15a5a3c8ddca1590551ab7a2
| Author: Matt Redfearn <matt.redfearn@mips.com>
| Date: Wed Apr 11 08:50:17 2018 +0100
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| lib: Rename compiler intrinsic selects to GENERIC_LIB_*
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Halt is not automatically executed if we start the kernel.
So, we may have potentially memory corruptions.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Currently the backlight implementation stretches a brightness change over
a period of 100ms. While this is a fine default for PWM backlights, a user
might wish to change this slew time to meet other constraints or even
completely disable it for some backlight devices.
Add a parameter and provide the default value from the backlight device.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patch is for convenience to set bkops-enable (EXT_CSD_BKOPS_EN[163])
on devices which have it not yet activated.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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If an attached bb device was removed before the actual mtd device
the code would try due to a missing pointer reset to access
the no more present bb device handle which leads to a page fault.
This bug was made visible by commit "7649473 mtd: nand: remove
automatically created bb devices" which relys on a correct
mtd->cdev_bb handling.
Signed-off-by: Heinrich Toews <heinrich.toews@wago.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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lseek checks for non-negative in-memory offsets (addresses), failing otherwise.
However negative address 0xffffffffXXXXXXXX is a valid MIPS64 virtual address.
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This file was last touched in 2014-12, 2010-07 and 2009-12 and has at
most historical value. Most of the open tasks are done, if not, they are
probably out of date anyway.
Signed-off-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patch came out of discussions in the 'MIPS parallel build breakage' e-mail thread:
http://lists.infradead.org/pipermail/barebox/2018-March/032251.html
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Unit number is added to the /memory nodes to fix this dtc warning:
Warning (unit_address_vs_reg): /memory: node has a reg or ranges
property, but no unit name
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Based on feedback from Sascha:
http://lists.infradead.org/pipermail/barebox/2018-April/032694.html
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skeleton.dtsi should no longer be used
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Several reasons to remove skeleton.dtsi are explained in
the linux commit 3ebee5a2e141 ("arm64: dts: kill skeleton.dtsi").
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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and define it as source of MAC address for ag71xx driver
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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and define it as source of MAC address for ag71xx driver
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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this partition contains calibration data for WiFi and
some board specific data, like MAC address.
For now we care only about MAC.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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