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| * | | | ARM: Layerscape: TQMLS1046a: Add environment and update handlersSascha Hauer2019-05-102-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TQMLS1046a can boot from QSPI and SD/MMC. Add partitioning for these devices and barebox environment / barebox update handlers on them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: Support booting from QSPISascha Hauer2019-05-102-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have to build correct images suitable for QSPI, thus have to call lspbl_spi_image instead of lspbl_image. In lowlevel code call the xload function which detects the bootsource rather than hardcoding SD/MMC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: unify pbi filesSascha Hauer2019-05-103-35/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This unifies the two different pbi files. With our approach for QSPI booting differences in the pbi files are not necessary: - We do not do execute in place for QSPI, so we do not need different image execution addresses - Setting up the QSPI clock doesn't hurt even for SD boot Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: print life signs when debuggingSascha Hauer2019-05-101-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do the UART initialization after the SoC specific lowlevel setup and print the usual '>' when early debuging is enabled. To let this go out properly it seems we have to wait a small amount of time beforehand. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: Sync qspi RCW from TQ U-BootSascha Hauer2019-05-101-4/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: configure qspi dividerSascha Hauer2019-05-101-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: ls1046a: Add bbu handlersSascha Hauer2019-05-101-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The barebox images can simply be written to the partitions, so we can use bbu_register_std_file_update() for updating to MMC and QSPI. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: ls1046a: Add automatic bootsource detection xload functionSascha Hauer2019-05-103-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper function which continues booting from the detected boot source. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: Add QSPI boot supportSascha Hauer2019-05-105-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting Layerscape from QSPI is a bit tricky and the approach we take is different from the one U-Boot has taken, so it's worth writing and reading the following explanation. The QSPI controller can map the Flash contents into the memory space (On LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this memory window. The Layerscape SoCs have a PowerPC history, so it seemed appropriate for the designers to let the QSPI controller operate in big endian mode by default. To let the SoC see the correct RCW we have to write the RCW and PBI data with be64 endianess. Our PBL image tool pokes the initial binary into the SoC internal SRAM using PBI data as done with SD/MMC boot aswell. barebox then changes the QSPI controller endianess to le64 to properly read the barebox binary (placed at an flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and jumps to it. U-Boot has another approach. Here the initial binary is executed in place directly at 0x40100000. This means the QSPI controller endianess must be swapped inside the PBI data. This has the effect that the whole RCW/PBI data must be 64bit endianess swapped *except* the very last word of the PBI data which contains the CRC command and is read already with changed endianess. As a conclusion when porting QSPI PBI files from U-Boot to barebox skip commands changing the endianess in the QSPI controller and make sure the image is executed in internal SRAM and not in the Flash memory window. Lines like this should be removed: 09550000 000f400c This sets the binary execution address: 09570604 40100000 For barebox it should be changed to 0x10000000. As a result the PBI files can probably be unified between SD and QSPI boot. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: pblimage: Drop pbl end commandSascha Hauer2019-05-101-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PBL image tool includes two commands into the image. These are executed after the initial image has been uploaded but before the final CRC check. These commands are "flush" and "wait". According to the reference manual a "flush" command can be used to read back the the value just written to CCSR register space in order to let the previous write complete. This seems unnecessary as the last write was never to the CCSR register space. The "wait" command also seems unnecessary as the time parameter is 0. As all this end_cmd stuff goes back to the PowerPC times and everything still seems to work on Arm let's just remove it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: ls1046a: Add bootsource detection supportSascha Hauer2019-05-103-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not much to do, there are only a few boot sources supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | esdhc-xload: invalidate icache before jumping to imageSascha Hauer2019-05-101-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | bbu: In bbu_register_std_file_update detect device before accessing itSascha Hauer2019-05-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device the standard file update handler writes to may not be present before detecting it, so as a first step detect it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | bbu: bbu_register_std_file_update should take const char*Sascha Hauer2019-05-102-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | String arguments to bbu_register_std_file_update should be const. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: defconfig: Enable more featuresSascha Hauer2019-05-091-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TQMLS1046a has an i2c mux and a i2c gpio expander. Add support for it and also disable early debugging as these are for a single board only. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | net: fsl-fman: Sync rx buffers for device initiallySascha Hauer2019-05-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rx buffers must be given to the device initially to work properly. Otherwise the first packets are corrupted. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | filetype: Detect Layerscape PBL imagesSascha Hauer2019-05-092-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Layerscape SoCs have their own boot image format. Add filetype detection for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: Fix pinmux setup for i2c4Sascha Hauer2019-05-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this the I2C mux on i2c4 works properly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: Unify SD and eMMC imagesSascha Hauer2019-05-083-97/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TQ has unified SD and eMMC images in their U-Boot. Do the same in barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: Update device tree files from tq repositorySascha Hauer2019-05-082-25/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update TQMLS1046a device tree files from TQ repository as of rocko.TQMLS1046A.BSP.SW.0002 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: Use static DDR settingsSascha Hauer2019-05-081-14/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TQ prefers static values in their U-Boot, so use these values in barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ddr: fsl: move fsl_ddr_set_memctl_regs prototype to include/Sascha Hauer2019-05-082-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fsl_ddr_set_memctl_regs() is not only used internally in the DDR controller driver, but can also be called by the boards to configure a static setting. Move the prototype to include/ where it can be used by board code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Layerscape: TQMLS1046a: Set cpo_sample valueSascha Hauer2019-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting the board issues the warning: WARN: pls set popts->cpo_sample = 0x48 So set the value to the desired value. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | mci: imx-esdhc-pbl: ls1046a: Set better divider valuesSascha Hauer2019-05-081-1/+1
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | MMC Frequency was set to something like 55MHz. This doesn't work for all SD cards. Set to 25MHz which is supported by all SD cards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/imx'Sascha Hauer2019-05-1018-50/+823
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| * | | | Documentation: imx: add documentation for RioTboardOleksij Rempel2019-05-061-0/+133
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | clk: vf610: improve handling case that cpu frequency can't be changedHeiner Kallweit2019-04-291-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we get a nasty error message if the cpu clock can't be changed: DDRC is clocked by PLL1, can't switch CPU clockinitcall vf610_switch_cpu_clock+0x1/0x198 failed: Invalid argument So let's do the following: - factor out the check from vf610_switch_cpu_clock_to_500mhz() and vf610_switch_cpu_clock_to_400mhz - if clock can't be changed, don't treat it as an error - don't call clock notifier chain if clock can't be changed - add trailing newline to the warning message Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: zii-vf610-dev: Add ZII SSMB DTU boardAndrey Smirnov2019-04-264-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Zodiac Digital Tapping Unit, a VF610 based network device with 5 Ethernet ports. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: zii-imx8mq-dev: Drop unnecessary barrier() in switch statementAndrey Smirnov2019-04-231-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AArch64 uses PC-relative addressing instead of absolute one for data lookups, so compiling switch statement into a LUT shouldn't be a problem regardless if relocation happened or not. Disassembly of PBL code looks almost exactly the same with or without this workaround, so it is clearly not needed. Drop it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: zii-imx51-rdu1: Use -fno-tree-switch-conversion -fno-jump-tablesAndrey Smirnov2019-04-232-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original and very poor workaround no longer works against GCC8, so drop it and replace with a proper solution that should've been used in the first place - specifying -fno-tree-switch-conversion -fno-jump-tables as CFLAGS when building lowlevel.c Tested to work with: - GCC 8.2.1 (arm-none-eabi) - GCC 7.1.0 (arm-none-eabi) - GCC 4.8.4 (armv7l-timesys-linux-gnueabihf) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: zii-vf610-dev: Use -fno-tree-switch-conversion -fno-jump-tablesAndrey Smirnov2019-04-232-17/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original and very poor workaround no longer works against GCC8, so drop it and replace with a proper solution that should've been used in the first place - specifying -fno-tree-switch-conversion -fno-jump-tables as CFLAGS when building lowlevel.c Tested to work with: - GCC 8.2.1 (arm-none-eabi) - GCC 7.1.0 (arm-none-eabi) - GCC 4.8.4 (armv7l-timesys-linux-gnueabihf) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | mtd: spi-nor: add Winbond W25Q40BWAlexander Kurz2019-04-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This 4MBit SPI chip can be found in Kindle Voyage devices Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: imx8mq: link PCIE1 and PCIE2 power domainsLucas Stach2019-04-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Those two power domains can only be used together. The link between the two has been dropped with the dts merge of v5.1-rc1. Fix this. Fortunately the i.MX8MQ PCIe support will land in Linux 5.2, so we can drop all those PCIe related local DT overrides with the next big dts upstream sync. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: Add missing quotes to HAB specific definesSascha Hauer2019-04-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale Code Signing Tool (cst) needs quotes around the filenames passed in the csf file. Add these quotes when the CONFIG_HAB* variables are passed from the command line. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | Add i.MX25 rtc driverSascha Hauer2019-04-123-0/+630
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a RTC driver for the Freescale i.MX25. This is done more to get access to the nonvolatile general purpose register than it is done to read the clock. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX25: Add some more clocksSteffen Trumtrar2019-04-122-1/+8
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some clocks needed for: - RNGB - SCC - Dryice RTC Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/dts'Sascha Hauer2019-05-1022-78/+142
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| * | | | dts: update to v5.1Sascha Hauer2019-05-101-6/+7
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | dts: update to v5.1-rc7Sascha Hauer2019-05-103-3/+8
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | dts: update to v5.1-rc6Sascha Hauer2019-05-102-2/+22
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | dts: update to v5.1-rc4Sascha Hauer2019-05-1016-67/+105
| | |/ / | |/| | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/ctrlc'Sascha Hauer2019-05-1011-107/+246
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| * | | | defaultenv: Convert init script to CSascha Hauer2019-04-242-98/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's hard to get more complicated things right in hush. This commit converts the /env/bin/init script to C code. With this we get a better error handling and better control what is being done. If /env/bin/init exists in the environment then it is still executed instead of the corresponding C code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | console_countdown: Add pattern listSascha Hauer2019-04-243-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an optional string argument to console_countdown() which can hold a list of keys which also abort the countdown. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | console: forbid ctrlc during startupSascha Hauer2019-04-243-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When global.autoboot_abort_key is set to ctrl-c then the user is expected to press ctrl-c to get to the prompt. The user might press ctrl-c before the init script runs the "timeout" command. In this case the init script is aborted at arbitrary places which leads to inconsistent results depending on the place it is aborted. This patch introduces the global.console.ctrlc_allowed variable. When this variable is set to false ctrl-c is ignored entirely. The variable is set to false by default and changed to true in the init script. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | Shell: Handle aborting loops betterSascha Hauer2019-04-245-8/+30
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's easy to get stuck in an infinite loop in the hush shell: while true; do sleep 1; done The 'sleep' command will check for ctrl-c with the ctrlc() function. This will abort the sleep command. Hush then checks for ctrl-c again in the loop. The ctrl-c in the buffer has already been eaten by the sleep command, so the loop will continue. With this patch we remember the presence of a ctrl-c character in a variable instead of checking for a new character each time. The variable must be resetted explicitly by calling ctrlc_handled() which will be called by the shell in the outer loop. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/blobgen'Sascha Hauer2019-05-1023-0/+1563
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| * | | | crypto: caam: add blobgen driverSteffen Trumtrar2019-04-124-0/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The blobgen driver allows generating and reading of red blobs on the i.MX6 CAAM crypto core. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | crypto: add new imx-scc driverSteffen Trumtrar2019-04-127-0/+694
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Security Controller (SCC) is found on (at least) i.MX25 SoCs. It is not a crypto engine in the usual sense. The only supported algorithm in hardware is 3DES and the key is not configurable, but is fused in the hardware. The SCC can be handed some block of data in the red memory space and it will return the encrypted data in the black memory space and vice versa. The API for this driver are the functions - mxc_scc_cbc_des_encrypt - mxc_scc_cbc_des_decrypt Along with this driver a blobgen implementation is provided. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | lib: add blobgen frameworkSteffen Trumtrar2019-04-127-0/+418
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a framework for en/decrypting data blobs. Some SoCs have support for hardware crypto engines that can en/decrypt using keys that a tied to the SoC and are visible for the crypto hardware only. With this patch it's possible to encrypt confidential data using these keys and to decrypt it later for usage. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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