| Commit message (Collapse) | Author | Age | Files | Lines |
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PCI BARs require their address to be at least aligned to their
size, otherwise address decoding will fail as the base address
gets rounded down.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Otherwise we may end up with a too low base address and push
requests for the upstream bus onto the downstream side.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The memory type may include other flags, so just check for
the 64bit allocation flag to see if the BAR is a 64bit one.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This makes diagnosing problems in address space allocation
much easier.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Driver "init" function might be called multiple times.
On every "init" Tx/Rx buffer descriptors are initialized: "descs_init"
-> "{tx|rx}_descs_init".
In its turn those init functions set MAC's "{tx|rx}desclistaddr" to
point on the first buffer descriptor in the list.
So CPU to start operation from the first buffer descriptor as well after
every "init" we have to reset "{tx|rx}_currdescnum".
[Original U-Boot patch by Alexey Brodkin <abrodkin@synopsys.com>]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.
[Original U-Boot patch by Alexey Brodkin <abrodkin@synopsys.com>]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Do not select MIIPORT for RGMII interface
[Original U-Boot patch by Vipin Kumar <vipin.kumar@st.com>]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There are a few registers where consecutive writes to the same location
should be avoided or have a delay.
According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.
GMAC Registers:
Registers 0-3 All bits
Registers 6-7 All bits
Register 10 All bits
Register 11 All bits except for 5-6.
Registers 16-47 All bits
Register 48 All bits except for 18-16, 14.
Register 448 Bit 4.
Register 459 Bits 0-3.
[Original U-Boot patch by Dinh Nguyen <dinguyen@altera.com>]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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It's pin mpp57 that has function vdd/cpu2-3-pd
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Linux changed several mpp names in commits:
438881dfddb9 (pinctrl: mvebu: armada-370: fix spi0 pin description)
bc99357f3690 (pinctrl: mvebu: armada-xp: remove non-existing NAND pins)
80b3d04feab5 (pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions)
100dc5d84095 (pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions)
7bd6a26db6f9 (pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins)
dae5597f253a (pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins)
d4974c16ed22 (pinctrl: mvebu: armada-{370,375}: normalize PCIe pins)
f32f01e1ba6b (pinctrl: mvebu: armada-{370,375}: normalize audio pins)
a361cbc575d6 (pinctrl: mvebu: armada-{370,xp}: normalize ethernet txclkout pins)
bfacb5669474 (pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet)
9e05db29e2ac (pinctrl: mvebu: armada-370: align spi1 clock pin naming)
50a7d13d2410 (pinctrl: mvebu: armada-xp: rename spi to spi0)
88b355f1e4e5 (pinctrl: mvebu: armada-xp: add spi1 function)
fb53b61d7768 (pinctrl: mvebu: armada-xp: add nand rb function)
b19bf3797679 (pinctrl: mvebu: armada-xp: add dram functions)
Adapt the barebox mvebu drivers accordingly.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The mvebu socs support up to 8 chip selects. Make use of them.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds tab completion for the clk_* commands.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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ksz8021_config_init() unconditionally sets the KSZPHY_OMSO_RMII_OVERRIDE
bit. This is since the initial micrel phy commit, so it's not
reproducible where this comes from and why this is done. Neither U-Boot
nor the kernel ever touch this bit and so should we. Also, instead
of doing a write only operation, read/modify/write the bit we actually
want to change.
This fixes operation on a KSZ8081MLX which is a MII only phy.
KSZPHY_OMSO_RMII_OVERRIDE is reserved here and must be written to 0.
KSZPHY_OMSO_MII_OVERRIDE is default 1 and must be written as 1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The chip selects are numbered 0..(max chip selects - 1). Chip select
with number <max chip selects> is invalid. Fix the check for that. Using
the out of bound chip select may hang your board.
Signed-off-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Make access to the mc13892 charger parameter voltage, current and max power
dissipation readable in terms of millivolts, milliamps and milliwatts.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This way the ethernet device will show up at the correct point
in the device hierarchy.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For builtin dtbs all compiled dtbs matching section .dtb.rodata.*
are collected in a single section. Since every dtb is compiled as
uncompressed and also as compressed binary each dtb ends up twice
in the section. Let's put the compressed variants in .dtbz.rodata.*
sections rather than .dtb.rodata.*.z so they end up in the binary
only once.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Daniel Krüger <daniel.krueger@systec-electronic.com>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The 'nv' command is often used to create a nv variable
for an existing global variable, so add a command completion
function for this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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linux/list.h needs linux/kernel.h for container_of(). Add it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The start_barebox() function is defined in the <common.h> header file.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Nearly identical to Linux-4.8 clock support, only some unnecessary
clocks skipped.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add functions to access the OCOTP fuses field wise, similar to what has
been done for the IIM. Also add a i.MX6 fusemap header file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Some consoles must be configured for DTE mode. Allow to set this
in lowlevel code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The defconfig files are long untouched and a
make xy_defconfig; make savedefconfig usually generates quite
a different looking file. Refresh them to make it easier to generate
patches against the configs using
make xy_defconfig; make menuconfig; make savedefconfig
This has been done with the following script.
for a in arch/*; do
arch=$(basename $a)
for c in $a/configs/*; do
config=$(basename $c)
export ARCH=$arch
make $config && make savedefconfig && mv defconfig $c
done
done
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The DCD NOP command is available for all flash header v2 devices (i.MX28,
50, 53, 6 and 7).
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We need to add the spi aliases to set the bus number correct in
the driver.
Delete the spi1 alias again in the am33xx-strip.dtsi for MLO as
the node is deleted there also.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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EEPROM information is needed in barebox.bin in order to setup MACs and
select appropriate DTB from kernel-fit.itb, so disable this initcall
in MLO.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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