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* soc: imx: gpcv2: Switch to SPDX identifierAndrey Smirnov2019-02-111-7/+1
| | | | | | | | | | | | | Port of a Linux commit 8d8e3b7d8f06f69005d829d4a195b00ef976004b Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* soc: imx: gpcv2: make pgc driver more generic for other i.MX platformsAndrey Smirnov2019-02-111-27/+41
| | | | | | | | | | | | | | | | | | | Port of a Linux commit 73f59712a1a3e532a2cbfe582ecfdbf56c33297d i.MX8MQ and i.MX8MM share same gpc module with i.MX7D, they can reuse gpcv2 pgc driver for power domain control, this patch renames all functions and structure definitions started with "imx7" to "imx", and use .data in imx_gpcv2_dt_ids[] to pass platform specific power domain data for power domain driver, thus make gpcv2 pgc driver more generic for i.MX platforms. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* soc: imx: gpcv2: use A_CORE instread of A7 for more i.MX platformsAndrey Smirnov2019-02-111-9/+9
| | | | | | | | | | | | | | | Port of a Linux commit fea88b2b80ab7a01982a6494ea8e8099cddc7b38 gpcv2 driver is NOT just used on i.MX7D which has Cortex-A7 cores, but also on i.MX8MQ/i.MX8MM platforms which use Cortex-A53 cores, so let's use A_CORE instread of A7 to avoid confusion. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: Add PCI fixups section to linker scriptAndrey Smirnov2019-02-111-0/+12
| | | | | | | | Add PCI fixups section to linker script, so it would be possible to enable PCI support. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Fix pointer width cast problemAndrey Smirnov2019-02-111-3/+3
| | | | | | | | | | | Casting to u32 works well on 32-bit builds, but causes problem when compiled on 64-bit machines. Switch it to cast to "unsigned long", so that it would have appropriate width in both cases. While at it, replace explicit casts to void * with IOMEM. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* net: fec_imx: skip fec_halt if the FEC wasn't startedLucas Stach2019-02-111-0/+7
| | | | | | | | | | | | | If the FEC driver is enabled, but the ethernet device was never opened due to booting from another source the wait for graceful transmit stop will always fail. This introduces an unnecessary boot delay and prints a distracting warning. As there is no point in trying to shut down the FEC if it was never started, just skip all of fec_halt in that case. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* scripts: imx-image: make read_file behaviour consistentSascha Hauer2019-02-111-13/+11
| | | | | | | | | | When read_file fails then it exits the program in most cases. Let's exit the program when stat() fails aswell, so that we *always* exit the program on failure. Drop all error handling for read_file since that's no longer necessary and rename the function to xread_file to make clear it won't fail. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* scripts: imx-image: Be more informative on open errorsSascha Hauer2019-02-111-4/+12
| | | | | | | | When opening a file fails then consistently print a message which file we cannot open and why. In one place no error checking was done at all, so add this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: Add support for ZII i.MX8MQ based devicesAndrey Smirnov2019-02-1118-2/+2081
| | | | | | | | | | | | | | Add support for the following ZII i.MX8MQ based boards: - ZII i.MX8MQ RMB3 - ZII i.MX8MQ Zest Most of the basic peripherals are supported by this patch. More advanced features such as PCIe, display support, etc, are planned to be added later. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8MQ: bbu: Add MMC boot handlerAndrey Smirnov2019-02-112-0/+14
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Documentation: i.MX: Increase :maxdepth: for board documentationAndrey Smirnov2019-02-111-1/+1
| | | | | | | | A number of board documentation file have subsections. Increase :maxdepth:, so we'd get proper TOC and numbering. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: drop the imx subdirLucas Stach2019-02-014-12/+12
| | | | | | | | | | We don't intend to ship any files in this directory, so there is no risk of the directory getting too crowded over time. Drop the subdir as this makes it easier for a outer build system to drop all the needed firmwares into the correct directory. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: add a note about license implicationsLucas Stach2019-02-011-0/+7
| | | | | | | | | Building additional firmware into the boot image has some license implications, which should be considered by the user, so add a short note about this. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: imx: remove prebuilt ATF binaryLucas Stach2019-02-011-0/+0
| | | | | | | | | | | | | | | | | | | | The prebuilt ATF binary is in fact a license compliance issue. While the used BSD-3-clause license allows aggregation with the Barebox binary, the chosen license requires us to ship the license text itself for the source distribution and also for the binary form if the built boot image contains the ATF binary. As this is a restriction that only applies to some boot images, depending on the Barebox configuration, it's non-trivial to do proper license compliance from within the Barebox source. Remove the prebuilt binary and rely on the external build system or user to provide the correct binary. Most system build systems already provide a proper way to handle the license dependency issue. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Documentation: imx8mq-evk: add instructions for HDMITX firmwareLucas Stach2019-02-011-2/+12
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Documentation: imx8mq-evk: point to current version of the firmwareLucas Stach2019-02-011-4/+4
| | | | | | | | There were some updates to the i.MX8MQ DDR training firmware, so better point to the current version. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Port imx6_pcie_ltssm_enable()Andrey Smirnov2019-01-181-9/+18
| | | | | | | Port imx6_pcie_ltssm_enable() from Linux kernel driver. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Drop unnecessary root_bus_nr settingAndrey Smirnov2019-01-181-1/+0
| | | | | | | | | | | | | | | | | | Port of a Linux commit 39f712e989c5e591c58b65b62981b85027ba3103 Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Fix spelling mistake: "contol" -> "control"Andrey Smirnov2019-01-181-2/+2
| | | | | | | | | | | | | Port of a Linux commit 7221547e55b7929e4d46983f6f3ca15f36ee4dac Trivial fix to spelling mistake in dev_err message Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <hongxing.Zhu@nxp.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Do not switch speed if Gen2 is disabledAndrey Smirnov2019-01-181-27/+28
| | | | | | | | | | | | | | | | | | Port of a Linux commit 93b226f9c65a951a91617f87ba1f05f14e59f26f Save a bit of time and avoid going through link speed change procedure in configuration where link max speed is limited to Gen1 in DT. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Do not wait for speed change on i.MX7Andrey Smirnov2019-01-181-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit e6dcd87fff69a9d454104b65569074855cf95b1e As can be seen from [1]: "...the different behavior between iMX6Q PCIe and iMX7D PCIe maybe caused by the different controller version. Regarding to the DOC description, the DIRECT_SPEED_CHANGE should be cleared after the speed change from GEN1 to GEN2. Unfortunately, when GEN1 device is used, the behavior is not documented. So, IC design guys run the simulation and find out the following behaviors: 1. DIRECT_SPEED_CHANGE will be cleared in 7D after speed change from GEN1 to GEN2. This matches doc’s description 2. set MAX link speed(PCIE_CAP_TARGET_LINK_SPEED=0x01) as GEN1 and re-run the simulation, DIRECT_SPEED_CHANGE will not be cleared; remain as 1, this matches your result, but function test is passed, so this bit should not affect the normal PCIe function." imx6_pcie_wait_for_speed_change() will report false failures for Gen1 -> Gen1 speed transition, so avoid doing that check and just rely on imx6_pcie_wait_for_link() only. [1] https://community.nxp.com/message/867943 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Allow probe deferral by reset GPIOAndrey Smirnov2019-01-181-8/+11
| | | | | | | | | | | | | | | | | | | | | Port of a Linux commit bde4a5a00e761f55be92f62378cf5024ced79ee3 Some designs implement reset GPIO via a GPIO expander connected to a peripheral bus. One such example would be i.MX7 Sabre board where said GPIO is provided by SPI shift register connected to a bitbanged SPI bus. To support such designs, allow reset GPIO request to defer probing of the driver. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Add code to support i.MX7DAndrey Smirnov2019-01-183-46/+125
| | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 9b3fe6796d7c0e0c2b87243ce0c7f4744c54efad Add various bits of code needed to support i.MX7D variant of the IP. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Cc: yurovsky@gmail.com Cc: Mark Rutland <mark.rutland@arm.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* reset: Mark local functions as staticAndrey Smirnov2019-01-181-4/+4
| | | | | | | | | There are no outside users of of_reset_control_get() or gpio_reset_control_get(), so mark them as static. This allows us to avoid "no previous prototype" warning as well. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* reset: Add i.MX7 SRC reset driverAndrey Smirnov2019-01-183-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit abf97755ae31aaaf35156438dd3036e96f66da83 Add reset controller driver exposing various reset faculties, implemented by System Reset Controller IP block. Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Linux commit 26fce0557fa639fb7bbc33e31a57cff7df25c3a0 was squashed here as well: reset: imx7: Fix always writing bits as 0 Right now the only user of reset-imx7 is pci-imx6 and the reset_control_assert and deassert calls on pciephy_reset don't toggle the PCIEPHY_BTN and PCIEPHY_G_RST bits as expected. Fix this by writing 1 or 0 respectively. The reference manual is not very clear regarding SRC_PCIEPHY_RCR but for other registers like MIPIPHY and HSICPHY the bits are explicitly documented as "1 means assert, 0 means deassert". The values are still reversed for IMX7_RESET_PCIE_CTRL_APPS_EN. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* soc: imx: Add GPCv2 power gating driverAndrey Smirnov2019-01-185-0/+327
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 03aa12629fc4f73acf28e519c9ee9cb1f5dd3706 Add code allowing for control of various power domains managed by GPCv2 IP block found in i.MX7 series of SoCs. Power domains covered by this patch are: - PCIE PHY - MIPI PHY - USB HSIC PHY - USB OTG1/2 PHY Support for any other power domain controlled by GPC is not present, and can be added at some later point. Testing of this code was done against a PCIe driver. Cc: yurovsky@gmail.com Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Linux commit 9e01e2d56db23485a75864b6aeee8e443f024ddb was squashed here as well: soc: imx: gpcv2: fix regulator deferred probe If a regulator requests a deferred probe, the power domain gets initialized twice. This leads to a list double add (without list debugging the kernel hangs due to the double add later): WARNING: CPU: 0 PID: 19 at lib/list_debug.c:31 __list_add_valid+0xbc/0xc4 list_add double add: new=c1229754, prev=c12383b4, next=c1229754. Initialize the power domain after we get the regulator. Also do not print an error in case the regulator defers probing. Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Fixes: 03aa12629fc4 ("soc: imx: Add GPCv2 power gating driver") Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Linux commit 3637f12faf507b0a4b8ac1e7115fc99583ab1db3 was squashed here as well soc: imx: gpcv2: correct PGC offset Correct MIPI/PCIe/USB_HSIC's PGC offset based on design RTL, the values in the Reference Manual (Rev. 1, 01/2018 and the older ones) are incorrect. The correct offset values should be as below: 0x800 ~ 0x83F: PGC for core0 of A7 platform; 0x840 ~ 0x87F: PGC for core1 of A7 platform; 0x880 ~ 0x8BF: PGC for SCU of A7 platform; 0xA00 ~ 0xA3F: PGC for fastmix/megamix; 0xC00 ~ 0xC3F: PGC for MIPI PHY; 0xC40 ~ 0xC7F: PGC for PCIe_PHY; 0xC80 ~ 0xCBF: PGC for USB OTG1 PHY; 0xCC0 ~ 0xCFF: PGC for USB OTG2 PHY; 0xD00 ~ 0xD3F: PGC for USB HSIC PHY; Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Fixes: 03aa12629fc4 ("soc: imx: Add GPCv2 power gating driver") Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: base: Port power management code from LinuxAndrey Smirnov2019-01-186-1/+345
| | | | | | | | | Port an extremely abridged version of power management/power domain code from Linux as a dependency of i.MX7D PCIe work. Currenlty only bare minimum of functionality is implemented. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* regulator: Port ANATOP driver from LinuxAndrey Smirnov2019-01-183-1/+172
| | | | | | | | Port a subset of Linux driver sufficient enough to support feature needed for PCIe on i.MX7. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* regulator: Assume probe deferral instead of missing regulatorAndrey Smirnov2019-01-181-1/+6
| | | | | | | | | | Don't report requested regulator (via of_regulator_get()) as non-existent if said regulator is missing from regulator list. Instead report it as probe deferral to give other, unprobed, drivers a chance to resolve this. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* base: driver: Drop redundant list_empty() checkAndrey Smirnov2019-01-181-4/+1
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* regulator: Add support for setting regulator's voltageAndrey Smirnov2019-01-183-0/+167
| | | | | | | | | Add code needed to implement regulator_set_voltage(). Currently only bare minmum needed for ANATOP driver (added in follow up commit) is supported. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* regulator: Port basic regmap regulator functionsAndrey Smirnov2019-01-183-2/+98
| | | | | | | | In order to be able to port Linux driver relying on this API, port various regmap related regulator function to Barebox. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* regulator: Convert drivers to use struct regulator_descAndrey Smirnov2019-01-184-9/+17
| | | | | | | | To simplify porting kernel code, port a very basic struct regulator_desc and convert all of the code to use it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx: add support for Udoo Neo fullUwe Kleine-König2019-01-1810-0/+215
| | | | | | | | | | | Original patch from Uwe Kleine-König, I fixed the review comments and the imxcfg file to use the udoo neo values. I also tested the support on the udoo neo full board. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: check for use of obsolete pblx-*Ahmad Fatoum2019-01-181-0/+4
| | | | | | | | | | | | | | pblx-* has been removed in 5a1a5ed253 ("ARM: images: use piggydata") and using it (e.g. because a patchset was rebased) results in a non-obvious: make[1]: *** No rule to make target 'images/*.pblx.*', \ needed by 'images/barebox-*.img'. Stop. Avoid this by explicitly failing with an error message whenever pblx-y or pblx- has been defined. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: pblx is now pblbSascha Hauer2019-01-181-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: Drop unnecessary fix_sizeSascha Hauer2019-01-162-3/+2
| | | | | | | | Now that we compile the compressed binary into the decompressor we no longer need fix_size but can use the linker to fill in the image size into the binary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx8mq: Add back memory controller nodeLucas Stach2019-01-162-2/+3
| | | | | | | | This was lost during conversion to use upstream device tree. Fixes: 29841dfa4b ("ARM: imx8mq: use upstream devicetree") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/ultrascale'Sascha Hauer2019-01-1517-0/+194
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| * zynqmp: enable macb Ethernet supportThomas Hämmerle2019-01-092-0/+2
| | | | | | | | | | Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: add support for Xilinx ZCU104 boardMichael Tretter2018-12-1014-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP) and the Xilinx ZCU104 board. Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL) already took care of initializing the RAM. Also for debug_ll, the UART is expected to be already setup correctly. Thus, you have to add the Barebox binary to a boot image as described in "Chapter 11: Boot and Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual". Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: aarch64: add ENTRY_PROC macro for arm64Michael Tretter2018-12-101-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | arm64 has no __naked__ attribute and the compiler adds a function prologue for saving x29 and x30 to the stack for all C functions. This includes functions defined using the ENTRY_FUNCTION macro. Therefore, the stack needs to be setup before entering a C function, which is not possible if the entry is a C function. Provide a macro to implement the entry in assembly to be able to setup the stack before entering the low level entry function. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: aarch64: compile with general-regs-onlyMichael Tretter2018-12-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Without this flag, gcc generates code to save the Q/V registers to the stack for handling the va_list in pr_print(). Saving the registers is useless, as the registers are never restored, but accessing the registers to save them hangs the CPU. Follow the Linux arch/arm64/Makefile and use the general-regs-only flag to prevent usage of floating point and Advanced SIMD register. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: lib64: .gitignore barebox.ldsMichael Tretter2018-12-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e1287b1a8b27 ("arm: rework lib directory to support arm64") restructured the lib directory and added the lib64 directory. It moved the existing .gitignore to the lib32 directory but didn't add a new .gitignore for lib64. Thus building Barebox for arm64 results in stray barebox.lds files. Copy the .gitignore from lib32 to lib64. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/risc-V'Sascha Hauer2019-01-1538-1/+1317
|\ \
| * | Documentation: add RISC-V docsAntony Pavlov2019-01-071-0/+91
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: add erizo_generic_defconfigAntony Pavlov2019-01-071-0/+51
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: erizo: add nmon image creationAntony Pavlov2019-01-072-0/+21
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: erizo: enable nmonAntony Pavlov2019-01-071-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: erizo: add DEBUG_LL supportAntony Pavlov2019-01-072-0/+34
| | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-26 11:59:07 +0000