summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Merge branch 'for-next/imx'Sascha Hauer2019-05-1018-50/+823
|\
| * Documentation: imx: add documentation for RioTboardOleksij Rempel2019-05-061-0/+133
| | | | | | | | | | Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: vf610: improve handling case that cpu frequency can't be changedHeiner Kallweit2019-04-291-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we get a nasty error message if the cpu clock can't be changed: DDRC is clocked by PLL1, can't switch CPU clockinitcall vf610_switch_cpu_clock+0x1/0x198 failed: Invalid argument So let's do the following: - factor out the check from vf610_switch_cpu_clock_to_500mhz() and vf610_switch_cpu_clock_to_400mhz - if clock can't be changed, don't treat it as an error - don't call clock notifier chain if clock can't be changed - add trailing newline to the warning message Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zii-vf610-dev: Add ZII SSMB DTU boardAndrey Smirnov2019-04-264-2/+26
| | | | | | | | | | | | | | | | Add the Zodiac Digital Tapping Unit, a VF610 based network device with 5 Ethernet ports. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zii-imx8mq-dev: Drop unnecessary barrier() in switch statementAndrey Smirnov2019-04-231-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | AArch64 uses PC-relative addressing instead of absolute one for data lookups, so compiling switch statement into a LUT shouldn't be a problem regardless if relocation happened or not. Disassembly of PBL code looks almost exactly the same with or without this workaround, so it is clearly not needed. Drop it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zii-imx51-rdu1: Use -fno-tree-switch-conversion -fno-jump-tablesAndrey Smirnov2019-04-232-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original and very poor workaround no longer works against GCC8, so drop it and replace with a proper solution that should've been used in the first place - specifying -fno-tree-switch-conversion -fno-jump-tables as CFLAGS when building lowlevel.c Tested to work with: - GCC 8.2.1 (arm-none-eabi) - GCC 7.1.0 (arm-none-eabi) - GCC 4.8.4 (armv7l-timesys-linux-gnueabihf) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zii-vf610-dev: Use -fno-tree-switch-conversion -fno-jump-tablesAndrey Smirnov2019-04-232-17/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original and very poor workaround no longer works against GCC8, so drop it and replace with a proper solution that should've been used in the first place - specifying -fno-tree-switch-conversion -fno-jump-tables as CFLAGS when building lowlevel.c Tested to work with: - GCC 8.2.1 (arm-none-eabi) - GCC 7.1.0 (arm-none-eabi) - GCC 4.8.4 (armv7l-timesys-linux-gnueabihf) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: spi-nor: add Winbond W25Q40BWAlexander Kurz2019-04-231-0/+1
| | | | | | | | | | | | | | This 4MBit SPI chip can be found in Kindle Voyage devices Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: imx8mq: link PCIE1 and PCIE2 power domainsLucas Stach2019-04-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Those two power domains can only be used together. The link between the two has been dropped with the dts merge of v5.1-rc1. Fix this. Fortunately the i.MX8MQ PCIe support will land in Linux 5.2, so we can drop all those PCIe related local DT overrides with the next big dts upstream sync. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX: Add missing quotes to HAB specific definesSascha Hauer2019-04-231-1/+1
| | | | | | | | | | | | | | | | The Freescale Code Signing Tool (cst) needs quotes around the filenames passed in the csf file. Add these quotes when the CONFIG_HAB* variables are passed from the command line. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * Add i.MX25 rtc driverSascha Hauer2019-04-123-0/+630
| | | | | | | | | | | | | | | | This adds a RTC driver for the Freescale i.MX25. This is done more to get access to the nonvolatile general purpose register than it is done to read the clock. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX25: Add some more clocksSteffen Trumtrar2019-04-122-1/+8
| | | | | | | | | | | | | | | | | | | | Add some clocks needed for: - RNGB - SCC - Dryice RTC Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/dts'Sascha Hauer2019-05-1022-78/+142
|\ \
| * | dts: update to v5.1Sascha Hauer2019-05-101-6/+7
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | dts: update to v5.1-rc7Sascha Hauer2019-05-103-3/+8
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | dts: update to v5.1-rc6Sascha Hauer2019-05-102-2/+22
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | dts: update to v5.1-rc4Sascha Hauer2019-05-1016-67/+105
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/ctrlc'Sascha Hauer2019-05-1011-107/+246
|\ \ \
| * | | defaultenv: Convert init script to CSascha Hauer2019-04-242-98/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's hard to get more complicated things right in hush. This commit converts the /env/bin/init script to C code. With this we get a better error handling and better control what is being done. If /env/bin/init exists in the environment then it is still executed instead of the corresponding C code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | console_countdown: Add pattern listSascha Hauer2019-04-243-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an optional string argument to console_countdown() which can hold a list of keys which also abort the countdown. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | console: forbid ctrlc during startupSascha Hauer2019-04-243-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When global.autoboot_abort_key is set to ctrl-c then the user is expected to press ctrl-c to get to the prompt. The user might press ctrl-c before the init script runs the "timeout" command. In this case the init script is aborted at arbitrary places which leads to inconsistent results depending on the place it is aborted. This patch introduces the global.console.ctrlc_allowed variable. When this variable is set to false ctrl-c is ignored entirely. The variable is set to false by default and changed to true in the init script. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | Shell: Handle aborting loops betterSascha Hauer2019-04-245-8/+30
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's easy to get stuck in an infinite loop in the hush shell: while true; do sleep 1; done The 'sleep' command will check for ctrl-c with the ctrlc() function. This will abort the sleep command. Hush then checks for ctrl-c again in the loop. The ctrl-c in the buffer has already been eaten by the sleep command, so the loop will continue. With this patch we remember the presence of a ctrl-c character in a variable instead of checking for a new character each time. The variable must be resetted explicitly by calling ctrlc_handled() which will be called by the shell in the outer loop. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/blobgen'Sascha Hauer2019-05-1023-0/+1563
|\ \ \
| * | | crypto: caam: add blobgen driverSteffen Trumtrar2019-04-124-0/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The blobgen driver allows generating and reading of red blobs on the i.MX6 CAAM crypto core. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | crypto: add new imx-scc driverSteffen Trumtrar2019-04-127-0/+694
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Security Controller (SCC) is found on (at least) i.MX25 SoCs. It is not a crypto engine in the usual sense. The only supported algorithm in hardware is 3DES and the key is not configurable, but is fused in the hardware. The SCC can be handed some block of data in the red memory space and it will return the encrypted data in the black memory space and vice versa. The API for this driver are the functions - mxc_scc_cbc_des_encrypt - mxc_scc_cbc_des_decrypt Along with this driver a blobgen implementation is provided. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | lib: add blobgen frameworkSteffen Trumtrar2019-04-127-0/+418
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a framework for en/decrypting data blobs. Some SoCs have support for hardware crypto engines that can en/decrypt using keys that a tied to the SoC and are visible for the crypto hardware only. With this patch it's possible to encrypt confidential data using these keys and to decrypt it later for usage. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | include: crypto: import ablkcipher struct from kernelSteffen Trumtrar2019-04-121-0/+27
| | | | | | | | | | | | | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
| * | | include: crypto: import des.h from kernelSteffen Trumtrar2019-04-121-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Import just the DES defines part from the v4.0 Linux Kernel crypto des header. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
| * | | lib: add base64 helpersSteffen Trumtrar2019-04-124-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Import the busybox-1.23.1 uuencode/base64 helper functions. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | crypto/caam: Add missing includeSascha Hauer2019-04-121-0/+1
| |/ / | | | | | | | | | | | | | | | | | | rng_self_test.c doesn't include the header file providing the prototypes for the functions it implements. Add the missing include. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/arm'Sascha Hauer2019-05-106-11/+80
|\ \ \
| * | | ARM: mmu: mark uncached regions as eXecute never on v7Ahmad Fatoum2019-04-293-9/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM Cortex-A Series Programmer's Guide notes[1]: > When set, the Execute Never (XN) bit in the translation table entry > prevents speculative instruction fetches taking place from desired > memory locations and will cause a prefetch abort to occur if execution > from the memory location is attempted. > > Typically device memory regions are marked as execute never to prevent > accidental execution from such locations, and to prevent undesirable > side-effects which might be caused by speculative instruction fetches. Heed the advice and mark uncached memory with the XN bit, when the CPU is >=v7. It's possible that there are SoCs that have a section shared between device memory and the on-chip RAM hosting the PBL. In such a section, every page except for the OCRAM's should be mapped XN, but as we know of no SoC with such an OCRAM layout, we ignore this possibility for now and let mmu_early_enable map sections only. [1]: 9.6.3 "Execute Never", Version 4.0 Suggested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: mmu: remove doubly defined macroAhmad Fatoum2019-04-291-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PMD_SECT_DEF_CACHED is defined along with PMD_SECT_DEF_UNCACHED in mmu.h, which is included two lines prior. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: cache-armv7: start invalidation from outer levelsAhmad Fatoum2019-04-291-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 25/4/19 11:57, Lucas Stach wrote: > [T]he sequence that could go wrong in Barebox is as follows: > 1. CPU core starts invalidating at L1 cache level > 2. HW prefetcher decides that a specific address should be brought into > the L1 cache. > 3. HW prefetcher finds a valid block for the requested address in L2 > cache and moves cached data from L2 to L1. > 4. Only now CPU core invalidates L2 cache. > > In the above sequence we now have invalid data in the L1 cache line. > The correct sequence will avoid this issue: > > 1. CPU core starts invalidating at L2 cache level > 2. HW prefetcher decides that a specific address should be brought into > the L1 cache. > 3. HW prefetcher sees invalid tags for the requested address in L2 > cache and brings in the data from external memory. > 4. CPU core invalidates L1 cache, discarding the prefetched data. > The ARM Cortex-A Series Programmer's Guide addresses this issue in the SMP-context[1]: > If another core were to access the affected address between those > two actions, a coherency problem can occur. Such problems can be avoided > by following two simple rules. > > * When cleaning, always clean the innermost (L1) cache first and then > clean the outer cache(s). > * When invalidating, always invalidate the outermost cache first and > the L1 cache last. The current code correctly iterates from inner to outer cache levels when flushing/cleaning (r8 == 0), invalidation (r8 == 1) occurs in the same direction though. Adjust the invalidation iteration order to start from the outermost cache instead. Equivalent C-Code: enum cache_op { CACHE_FLUSH = 0, CACHE_INVAL = 1 }; register enum cache_op operation asm("r8"); register int i asm("r12"); register int limit asm("r3") = max_cache_level << 1; // e.g. 4 with L2 max +if (operation == CACHE_FLUSH) { i = 0; +} else { + i = limit - 2; +} bool loop_again; do { /* [snip] */ + if (operation == CACHE_FLUSH) { i += 2; loop_again = limit > i; + } else { + loop_again = i > 0; + i -= 2; + } } while (loop_again); [1]: 18.6 "TLB and cache maintenance broadcast", Version 4.0 Suggested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: cache-armv7: work around Cortex-A7 erratum 814220Ahmad Fatoum2019-04-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on 0e9a87bb from the linux-imx kernel: ------------------------------------------------------------------------------ | ARM/MP: 814220—B-Cache maintenance by set/way operations can execute | out of order. | | Description: | The v7 ARM states that all cache and branch predictor maintenance operations | that do not specify an address execute, relative to each other, in program | order. However, because of this erratum, an L2 set/way cache maintenance | operation can overtake an L1 set/way cache maintenance operation, this would | cause the data corruption. | | This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. | | This patch is the SW workaround by adding a DSB before changing cache levels | as the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation. | Signed-off-by: Jason Liu <r64343@freescale.com> ------------------------------------------------------------------------------ It was later posted to LKML for Linux inclusion, but is not yet mainline: <20190214083145.15148-1-benjamin.gaignard@linaro.org> Unlike the Linux version, we don't make the barrier dependent on a Kconfig option and always execute the dsb: On 25/4/19 12:02, Lucas Stach wrote: > I don't think we need a Kconfig option here. This function is not > really performance critical. The short pipeline stall introduced by the > dsb when switching the cache level is minor compared to the time it > takes to actually move the cache blocks on a clean. > > Just always execute the [dsb] and add a comment on why it is needed. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init()Andrey Smirnov2019-04-262-0/+27
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3, SCTLR will be in a state we expect it to be. Add code to reset it to a known state, so we'd always start form clean slate. This is also matches what we've been doing non 64-bit ARMs. Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon appear to have different mask ROM behaviour where it now leaves MMU enabled if no valid boot source is found. Page table it sets up doesn't include DDR range, so trying to bootstrap the device via JTAG/OpenOCD results in an abort. The value for SCTLR_ELx_FLAGS was taken from Linux kernel. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | / Release v2019.05.0v2019.05.0Sascha Hauer2019-05-101-1/+1
| |/ |/| | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: aarch64: do not use 32bit optimized find bit functionsMichael Tretter2019-05-062-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The optimized find bit functions are only implemented for 32 bit and are not built on aarch64 systems. Therefore, for example bootchooser cannot be build for aarch64. Select the generic find_bit implementations on aarch64. As the decision, if lib64 or lib32 is build or not, directly depends on CPU_V8, the generic implementation also should be used if CPU_V8 is selected. Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: zii-imx8mq-dev: select ZII_COMMONLucas Stach2019-05-061-0/+1
| | | | | | | | | | | | | | | | | | The RDU3 shares some of the board fixups with the other Zii boards. For those to work ZII_COMMON needs to be enabled. Fixes: d76ba38a1605 (ARM: zii-common: reuse i210 config check for RDU3) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: imx: disable IPU QoS setup for correct SoCsRouven Czerwinski2019-05-061-1/+1
|/ | | | | | | | | | | | | | | | | | The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL"), but instead it bails at the Solo, not the SX and SL. The original intent was most probably to add an exception for the i.MX6 Solo as well, so everything else is skipped, including the SX, SL and now the UL and ULL. Fix the code to reflect this. On the SX, SL, UL, ULL, this now avoids writes to memory, which isn't described in the datasheets. On the S, it now configures the QoS settings. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* hab/caam: Fix compilation of caam driver when hab is disabledSascha Hauer2019-04-113-6/+13
| | | | | | | | | The caam driver needs the variable habv4_need_rng_software_self_test, but this is only declared when HABV4 is enabled. Instead of exporting a variable rather provide a function to test if a software selftest of the random number generator is needed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* hab: habv4_need_rng_software_self_test is needed without hab supportSascha Hauer2019-04-111-1/+2
| | | | | | habv4_need_rng_software_self_test Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: socfpga: fix compiler warnings for Cyclone5Ian Abbott2019-04-101-3/+3
| | | | | | | | | | | | | | | When building for Cyclone5 SoCFPGA, the socfpga_a10_pll_init(), socfpga_a10_perith_init() and socfpga_a10_gate_init() functions are defined as dummy functions returning ERR_PTR(-ENOSYS). They are defined with external linkage. With '-Wmissing-prototypes' GCC warns about externally linked function definitions with no preceding prototype. Define them as 'static inline' to avoid the compiler warnings. (Note: Arria10 uses non-dummy versions of these functions declared 'extern' but defined elsewhere.) Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynqmp'Sascha Hauer2019-04-0914-3/+1344
|\
| * ARM: zynqmp: switch to firmware clock driverMichael Tretter2019-03-182-0/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | In the device tree, the clock controller is a subnode of the firmware node. Devices refer to the clocks by an id that is shared between the ATF and the driver. While the bindings for the clock controller are already upstream, the device in mainline Linux does not use them, yet. Add them in the Barebox device tree for now. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: add firmware DT nodeThomas Haemmerle2019-03-182-0/+18
| | | | | | | | | | | | | | | | | | Add firmware DT node in ZynqMP device tree. This node uses bindings as per new firmware interface driver. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: add ZynqMP clock driverMichael Tretter2019-03-188-0/+1162
| | | | | | | | | | | | | | | | | | | | | | | | The ZynqMP has a platform management unit (PMU) that is responsible for managing the clocks. Therefore, the clock driver uses the firmware driver to control the clocks. The Barebox driver is based on the Linux driver, but contains deviations to make the driver more readable and more consistent. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: move PAYLOAD_ARG_CNT to firmware headerMichael Tretter2019-03-182-2/+2
| | | | | | | | | | | | | | | | In order to use the query() call, the users of the firmware driver need to know the number of arguments. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: populate zynqmp_firmware dt nodeThomas Haemmerle2019-03-181-0/+1
| | | | | | | | | | | | | | | | | | | | The zynqmp_firmware node has sub-nodes for the various APIs to expose the platform management, as e.g. clock management. Therefore, the driver must populate the subnodes to initialize these drivers. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * of: populate "/firmware" while populating device treeThomas Haemmerle2019-03-181-1/+5
| | | | | | | | | | | | | | | | | | | | | | The sub-nodes of "/firmware" are not populated, since it has no "compatible" property. Copy the behavior of Linux and call of_platform_populate() on the "/firmware" node to probe firmware drivers. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-23 09:43:41 +0000