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* ARM: stm32mp: select ARM_USE_COMPRESSED_DTB for the whole archAhmad Fatoum2019-11-071-0/+1
| | | | | | | | We'll probably be using compressed DTBs for all new boards as well, thus move the ARM_USE_COMPRESSED_DTB, so it's always selected for STM32MP. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: implement PSCI client driverAhmad Fatoum2019-11-071-0/+9
| | | | | | | | | | | | System reset on the STM32MP may be done via PSCI when running TF-A as first-stage boot loader. Provide a PSCI driver to simplify using it: - A psci_invoke function is exported, so other code can use it - A fixup for the PSCI device tree node is registered - A reset and poweroff handler via PSCI is registered for PSCI >= v0.2 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: select ARM_SMCCC alwaysAhmad Fatoum2019-11-061-0/+1
| | | | | | | | | ARM_SMCCC compiles in the code for issuing ARM secure monitor calls. We need those on the STM32MP, because barebox runs in non-secure mode and does some operations like reading the BSEC OTP through SMCs. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: sm: document SMC/PSCI related optionsAhmad Fatoum2019-11-061-1/+5
| | | | | | | | At least to me, the difference between these options were confusing at first. Clear this up. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: enable ARM_AMBAOleksij Rempel2019-11-061-0/+1
| | | | | | | It is needed for mci/sd/mmc driver. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: select ARCH_HAS_RESET_CONTROLLERAhmad Fatoum2019-11-061-0/+1
| | | | | | | | | Many STM32 peripherals, including I2C, SPI, USB and SDMMC use the RCC reset controller for reset. Enable ARCH_HAS_RESET_CONTROLLER, so drivers depending on RESET_CONTROLLER become available for selection. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mxs'Sascha Hauer2019-10-171-0/+1
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| * ARM: mxs: Move HAVE_PBL_MULTI_IMAGES up to ARCHSascha Hauer2019-10-021-0/+1
| | | | | | | | | | | | | | Now that all boards in mach-mxs select HAVE_PBL_MULTI_IMAGES we can move it up to ARCH_MXS. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/at91'Sascha Hauer2019-10-171-1/+0
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| * | pinctrl: add gpio and pinctrl driver for sama5d2 PIO4Ahmad Fatoum2019-10-141-1/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | The sama5d2 features a GPIO and pin controller different than the one we support in barebox. The device tree bindings are different as well, so it makes sense to have a separate driver for it. Add the pin control and GPIO driver as well as some helpers usable from PBL, should we want to do pinmuxing that early. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: drop bultin DTBSascha Hauer2019-10-011-14/+0
| | | | | | | | | | | | | | | | We can build multiple DTBs into the binary and board code can select which one to use. Drop the single builtin DTB and let the boards using it pass the correct one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: NETX: remove architectureSascha Hauer2019-09-231-5/+0
|/ | | | | | | NETX support has been removed from the Kernel, so there's no point in supporting it in barebox any longer. Remove the architecture. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/qemu'Sascha Hauer2019-09-121-0/+18
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| * ARM: Add generic device tree 2nd stage supportSascha Hauer2019-08-191-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for building a barebox image that boots with the Linux ARM Kernel booting convention. Support for this image can be enabled in Kconfig. It picks up a device tree passed in r2. This new image helps for example with qemu. It can be started with: qemu-system-aarch64 -m 2G -M virt -kernel images/barebox-dt-2nd.img -cpu cortex-a57 -serial stdio or: qemu-system-arm -m 1G -M sabrelite -kernel images/barebox-dt-2nd.img -nographic -dtb arch/arm/dts/imx6q-sabrelite.dtb Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Kconfig: create Kconfig symbol for ARCH_HAS_DATA_ABORT_MASKAhmad Fatoum2019-08-301-0/+1
| | | | | | | | | | | | | | | | Other arch-specific features are exposed in Kconfig too, so do here likewise. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Kconfig: create Kconfig symbol for ARCH_HAS_STACK_DUMPAhmad Fatoum2019-08-301-0/+1
|/ | | | | | | | Other arch-specific features are exposed in Kconfig too, so do here likewise. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: fix some misnomers/typosAhmad Fatoum2019-07-151-1/+1
| | | | | | | | | The arch was renamed to stm32mp, so it doesn't look out of place when the stm32mp2 is released. Fix spotted comments/labels with the old name. While at it, fix a typo about the SoC name on the DK2 board. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pinctrl: add driver for STM32 GPIO and pin multiplexerAhmad Fatoum2019-06-201-0/+1
| | | | | | | | | | | | | This adds driver support for the 12 GPIO banks on the STM32MP157. As they are accessible to both the Cortex-A cores as well as the Cortex-M core, modifications to these are protected by a hardware spinlock and clocks are enabled/disabled as required. All register fiddling done by the driver is collected in <soc/stm32/gpio.h>, so future PBL code may make use of it as well to chainload barebox proper. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp1: rename to stm32mpAhmad Fatoum2019-06-131-2/+2
| | | | | | | | | | | | Serial and clk driver both depend on CONFIG_ARCH_STM32MP1, so either the Kconfig symbol or their depend needs to change. Patches posted by the vendor to Linux, U-Boot and their BSP Yocto-Layer speak of a STM32MP-Family of which the STM32MP1 is the first series, thus rename the arch by dropping the 1. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: factor out of_psci_fixup() to separate fileSascha Hauer2019-05-131-0/+4
| | | | | | | | | of_psci_fixup() can be used by code which doesn't use the barebox psci implementation, but provides its own PSCI compatible firmware. Factor it out to a separate file to compile it independently of the barebox PSCI implementation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32'Sascha Hauer2019-04-091-0/+11
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| * ARM: Add initial STM32MP1 supportSascha Hauer2019-03-131-0/+11
| | | | | | | | | | | | | | | | | | | | | | This adds initial STMicroelectronics MP1 support along with support for the DK2 devel board. Only very basic support: - UART - SDRAM memory base/size - No 1st stage support Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2019-04-091-26/+26
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| * | treewide: surround Kconfig file paths with double quotesMasahiro Yamada2019-03-211-25/+25
| |/ | | | | | | | | | | | | | | | | Based on Linux commit 8636a1f9677db4f883f29a072f401303acfc2edd This will be needed when you sync Kconfig with Linux 5.0 or later. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: Add Layerscape clk supportSascha Hauer2019-03-131-0/+3
| | | | | | | | | | | | | | | | | | | | This adds support for the clock controller found on Layerscape SoCs. This is mostly an adoption of the corresponding Linux driver. This is tested on the LS1046a SoC. Other ARM based Layerscape SoCs should work aswell, support for the PowerPC based SoCs has been removed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Add basic Layerscape supportSascha Hauer2019-03-131-0/+7
|/ | | | | | | | | | This adds basic Layerscape support: - Makefile/Kconfig - Register maps - errata workarounds Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware-zynqmp: port from linuxThomas Haemmerle2019-02-271-0/+1
| | | | | | | Port Xilinx Zynq MPSoC Firmware layer driver from linux. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zynqmp: select macb driverThomas Haemmerle2019-01-301-0/+1
| | | | | | | macb supports Xilinx ZynqMP GEM, so select HAS_MACB by default. Signed-off-by: Thomas Haemmerle <thomas.haemmerle1988@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zynqmp: add support for Xilinx ZCU104 boardMichael Tretter2018-12-101-0/+14
| | | | | | | | | | | | | | Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP) and the Xilinx ZCU104 board. Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL) already took care of initializing the RAM. Also for debug_ll, the UART is expected to be already setup correctly. Thus, you have to add the Barebox binary to a boot image as described in "Chapter 11: Boot and Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual". Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kconfig: include common Kconfig files from top-level KconfigAntony Pavlov2018-12-031-9/+0
| | | | | | | | | | | | | Based on this linux kernel commit: > commit 1572497cb0e6d2016078bc9d5a95786bb878389f > Author: Christoph Hellwig <hch@lst.de> > Date: Tue Jul 31 13:39:30 2018 +0200 > > kconfig: include common Kconfig files from top-level Kconfig Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2018-08-131-4/+0
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| * ARM: socfpga: Arria10: support programming FPGA in PBLSteffen Trumtrar2018-08-081-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Arria10 boards don't have the FPGA programmed externally. Instead barebox needs to do that. As the Arria10 has the SDRAM controller in the FPGA, the first thing we need to do is, configure the FPGA before the SDRAM can even be used. It works like this: 1. boot ROM fetches the PBL from MMC 2. read the MBR from MMC (this depends on the setup done by the boot ROM) 3. read the Bitstream from the MMC and program the FPGA 4. re-read the barebox image from MMC, this time with the full barebox that is appended to the PBL 5. jump into the full barebox Only supported boot device is eMMC. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Add code to support SMCCC on AArch64Andrey Smirnov2018-08-081-0/+4
|/ | | | | | | | | | | | | | Port SMCCC code from Linux kernel. To accomodate that: - Introduce CONFIG_ARM_SMCCC, to allow enabling the code independent of CONFIG_ARM_SECURE_MONITOR - Bring <linux/arm-smccc.h> in - Add necessary constants to arch/arm/asm-offsets.c Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2018-06-111-1/+1
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| * scripts: create a separate section for host toolsUwe Kleine-König2018-06-111-1/+0
| | | | | | | | | | | | | | | | | | | | This allows to enable host tools even if they are not needed for the current configuration to improve compile coverage and simplify packaging these tools. The conversion doesn't cover all tools available but can be extended later. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * Add builtin firmware supportSascha Hauer2018-06-081-0/+1
| | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [andrew.smirnov@gmail.com: Add dummy.o in case directory is empty] Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: lib64: Make string functions aware of MMU configurationAndrey Smirnov2018-06-111-0/+7
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimized version of memset() in memset.S if called as: memset(foo, 0, size) will try to explicitly zero out data cache with: dc zva, dst which will result in Alignement Exception (DABT) if MMU is not enabled. For more info see: - C4.4.8 "DC ZVA, Data Cache Zero by VA" - D5.2.8 "The effects of disabling a stage of address translation" in "ARM Architecture Reference Manual. ARMv8, for ARMv8-A architecture profile" In similar vein, using optimized version of memcpy() could lead to a unaligned 16-byte write (using 'stp'), which is not allowed for Device-nGnRnE type of memory (see D5.2.8) and would liead to Alignement Exception. To fix both problems expose non-optimized and optimzied versions of the function and created a wrapper to dispatch the call to either one based on if MMU is enabled or not. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: hide some config optionsSascha Hauer2018-03-291-1/+2
| | | | | | | EABI and ATAGS have no meaning on aarch64, so hide the options from the user. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: For relocatable image force TEXT_BASE 0x0Sascha Hauer2018-03-211-1/+5
| | | | | | | Nothing else should be used for the relocatable image case, so force TEXT_BASE to 0x0 and do not show it in the menu. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add arria10 supportSteffen Trumtrar2017-05-031-3/+3
| | | | | | | | | | | | | | | | | | Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2017-04-071-3/+0
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| * ARM: mvebu: remove obsolete selectUlrich Ölmann2017-03-301-1/+0
| | | | | | | | | | | | | | | | This is a user choice now and has been removed for all other boards in commit 790980bf18af ("Make generic default environment type a use choice"). Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * poweroff: Allow to register poweroff handlersSascha Hauer2017-03-301-2/+0
| | | | | | | | | | | | | | | | | | | | Allow to register handlers for poweroff. This allows to have multiple poweroff implementations in a single binary. The implementation is close to the restart handlers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | at91sam9x5ek: Convert to mult-image buildAndrey Smirnov2017-03-301-1/+0
| | | | | | | | | | | | | | | | Convert AT91SAM9X5-EK board code to multi-image build process, similar to how majority of i.MX board code is built. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: Port at91 DT clock codeAndrey Smirnov2017-03-301-0/+1
|/ | | | | | | | Port at91 DT clock code from Linux 4.9-rc3. Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rpi'Sascha Hauer2017-03-131-17/+12
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| * ARM: rpi: switch to DT probe and multi-image buildLucas Stach2017-03-021-18/+12
| | | | | | | | | | | | | | | | This commit switches the RaspberryPi arch over to probe Barebox from the builtin DT and enables multi-image builds. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: rpi: always build relocatable imageLucas Stach2017-03-021-0/+1
| | | | | | | | | | | | | | | | Makes more space available for the malloc area and will allow to switch to multi-image later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mvebu'Sascha Hauer2017-03-131-0/+1
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| * | mvebu: get initial position of register window from image headerUwe Kleine-König2017-03-021-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | A problem when using 2nd stage booting on mvebu is that the first bootloader already switched the register window location from 0xd0000000 to 0xf1000000 by writing to 0xd0000080. When the second bootloader also tries to do this switch it writes to the wrong location resulting in an exception and so a boot failure. For this reason the base address of the register window is passed in the barebox header and picked up from there by early code. In a further patch bootm is taught to put the actual position of the window there for the second bootloader to finally make second stage booting work. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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