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* ARM: Rockchip: Add rk3568 supportSascha Hauer2021-06-281-3/+0
| | | | | | | | | This adds basic support for the Rockchip rk3568 SoC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-8-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-8-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Add atf common supportSascha Hauer2021-06-241-0/+3
| | | | | | | | | | | | ARM trusted firmware has some common data structures passed to bl31. This patch imports the code supporting this taken from U-Boot. The defines and data structures are taken directly from U-Boot, the support code is heavily modified for the sake of readability. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-9-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: make ARM_USE_COMPRESSED_DTB available for other archesAhmad Fatoum2021-03-231-3/+2
| | | | | | | | | | Other PBL-enabled architecture can benefit from compressed dtbs as well. Move symbol and code to a comm place to be able to use it from RISC-V in a later commit. In order not to break out of tree boards at runtime, the old symbol name is maintained for ARM. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: make BOARD_ARM_GENERIC_DT available for other archesAhmad Fatoum2021-03-231-1/+1
| | | | | | | | | | | Other architectures would benefit from the generic DT image too. Add a new arch-agnostic symbol that arches besides ARM can select. The new symbol itself should not have a prompt as the help text for each architecture likely differs (e.g. device tree handoff register). Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/bthreads'Sascha Hauer2021-03-231-0/+1
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| * ARM: asm: setjmp: implement coroutine dependency initjmp()Ahmad Fatoum2021-03-171-0/+1
| | | | | | | | | | | | | | Implement initjmp() for use with the incoming bthread support. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/arm-qemu-virt64'Sascha Hauer2021-03-231-4/+15
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| * | ARM64: qemu-virt64: migrate to generic DT imageAhmad Fatoum2021-03-171-4/+15
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current qemu-virt64 barebox support doesn't look much like what's offered on physical boards. It's not relocatable, lacks PBL and doesn't use device tree. As qemu-system-aarch64 -M virt -kernel already supplies an external device tree, we could just replace all existing support with BOARD_ARM_GENERIC_DT, which builds a barebox image that reuses an externally passed device tree. The 32-bit ARM VIRT support has some board code for host name setting and overlay applying to handle environment and state on flash. We could do without that, given the new virtio-blk support, but the code is already there, so reuse it and drop all current virt64-specific board code. As the barebox ELF image resulting from the build can no longer be directly booted as before and only with -kernel, not -bios, rename the Kconfig symbol, so existing users can notice this during build. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/arch-remove'Sascha Hauer2021-03-231-12/+0
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| * | ARM: remove Calxeda Highbank supportSascha Hauer2021-03-221-12/+0
| |/ | | | | | | | | | | | | | | | | | | Calxeda went out off business back in 2013. The Calxeda Highbank port did not get any active maintenance since then. Since the Highbank support plays some tricks with devices trees passed to barebox from the firmware it becomes a maintenance burden. Remove Highbank support altogether. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / bcm283X: Select OF clock providersUwe Kleine-König2021-03-151-0/+1
|/ | | | | | | | | | This makes available the fixed clock needed on rpi3 for USB. USB stopped working when the dwc driver started to require an otg clock. Fixes: f73ca701bb85 ("usb: dwc2: add clk dependency for probe via oftree") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: qemu: add support for qemu virt platformRouven Czerwinski2020-11-121-1/+1
| | | | | | | | | | Necessary support to boot barebox on ARM qemu virt platforms. No internal device tree, since it is passed by qemu. Therefore it employs the generic 2nd stage image as the low level code and only adds a virt specific board driver. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: vexpress: move Options to ARCH_VEXPRESSRouven Czerwinski2020-11-121-0/+5
| | | | | | | | | In preparation for the qemu virt image, move the KConfig options from MACH_VEXPRESS to ARCH_VEXPRESS. Also remove the choice, since we allow multiple boards to be selected with HAVE_PBL_MULTI_IMAGES. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Add KASan supportSascha Hauer2020-09-221-0/+2
| | | | | | | | | | | | | | This adds KASan support to the ARM architecture. What we are doing is: * Add __no_sanitize_address attribute to various lowlevel functions which do not run in a proper C environment * Add non-instrumented variants of memset/memcpy (prefixed with '__') * make original memcpy/memset weak symbols so strong definitions in lib/kasan/common.c can replace them * Use non-instrumented memcpy in early functions * call kasan_init() Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: module: Allow modules outside of bl rangeDavid Dgien2020-07-011-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | Unlike the Linux kernel, barebox does not have a dedicated heap for storing modules. Therefore, if the system memory configuration places the general heap further away than can be reached by a 'bl' instruction (24 bits of address, or 16 MiB), then the module relocations will fail due to being out of range. Allocate PLTs when loading modules so that jumps and calls whose targets are too far away for their relative offsets to be encoded in the instructions themselves can be bounced via veneers in the module's PLT. The modules will use slightly more memory, but after rounding up to page size, the actual memory footprint is usually the same. Adoption of Linux commits: 66e94ba3c8ea ARM: kernel: avoid brute force search on PLT generation 1031a7e674d1 ARM: kernel: sort relocation sections before allocating PLTs 05123fef0982 ARM: kernel: allocate PLT entries only for external symbols 35fa91eed817 ARM: kernel: merge core and init PLTs 7d485f647c1f ARM: 8220/1: allow modules outside of bl range Signed-off-by: David Dgien <dgienda125@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynq'Sascha Hauer2019-12-101-0/+1
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| * ARM: zynq: add trivial image build mechanismLucas Stach2019-11-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Currently this just calls the zynq_mkimage script to stamp in the header checksum. Can be extended to a proper multi-image build later on. This requires a PBL to be build, but as the only supported Zynq board already selects the PBL option in the defconfig there is no big change to the previous status Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/randfixes'Sascha Hauer2019-12-101-0/+4
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| * | ARM: layerscape: select OFTREE and OFDEVICELucas Stach2019-12-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The Layerscape architectures probes exclusively from DT, so make sure the correct config options are enabled. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: ARM_SMCCC is only available on >= ARMv7Lucas Stach2019-12-021-0/+2
| |/ | | | | | | | | | | | | | | So anything selecting this option must depend on those CPU architectures. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / PCI: Add layerscape PCIe driverSascha Hauer2019-11-271-0/+1
|/ | | | | | | | This adds support for the designware based PCIe controller found on Layerscape SoCs. The driver is based on Linux-5.4. The device tree fixups have been taken from U-Boot 2019.10. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: select ARM_USE_COMPRESSED_DTB for the whole archAhmad Fatoum2019-11-071-0/+1
| | | | | | | | We'll probably be using compressed DTBs for all new boards as well, thus move the ARM_USE_COMPRESSED_DTB, so it's always selected for STM32MP. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: implement PSCI client driverAhmad Fatoum2019-11-071-0/+9
| | | | | | | | | | | | System reset on the STM32MP may be done via PSCI when running TF-A as first-stage boot loader. Provide a PSCI driver to simplify using it: - A psci_invoke function is exported, so other code can use it - A fixup for the PSCI device tree node is registered - A reset and poweroff handler via PSCI is registered for PSCI >= v0.2 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: select ARM_SMCCC alwaysAhmad Fatoum2019-11-061-0/+1
| | | | | | | | | ARM_SMCCC compiles in the code for issuing ARM secure monitor calls. We need those on the STM32MP, because barebox runs in non-secure mode and does some operations like reading the BSEC OTP through SMCs. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: sm: document SMC/PSCI related optionsAhmad Fatoum2019-11-061-1/+5
| | | | | | | | At least to me, the difference between these options were confusing at first. Clear this up. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: enable ARM_AMBAOleksij Rempel2019-11-061-0/+1
| | | | | | | It is needed for mci/sd/mmc driver. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: select ARCH_HAS_RESET_CONTROLLERAhmad Fatoum2019-11-061-0/+1
| | | | | | | | | Many STM32 peripherals, including I2C, SPI, USB and SDMMC use the RCC reset controller for reset. Enable ARCH_HAS_RESET_CONTROLLER, so drivers depending on RESET_CONTROLLER become available for selection. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mxs'Sascha Hauer2019-10-171-0/+1
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| * ARM: mxs: Move HAVE_PBL_MULTI_IMAGES up to ARCHSascha Hauer2019-10-021-0/+1
| | | | | | | | | | | | | | Now that all boards in mach-mxs select HAVE_PBL_MULTI_IMAGES we can move it up to ARCH_MXS. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/at91'Sascha Hauer2019-10-171-1/+0
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| * | pinctrl: add gpio and pinctrl driver for sama5d2 PIO4Ahmad Fatoum2019-10-141-1/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | The sama5d2 features a GPIO and pin controller different than the one we support in barebox. The device tree bindings are different as well, so it makes sense to have a separate driver for it. Add the pin control and GPIO driver as well as some helpers usable from PBL, should we want to do pinmuxing that early. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: drop bultin DTBSascha Hauer2019-10-011-14/+0
| | | | | | | | | | | | | | | | We can build multiple DTBs into the binary and board code can select which one to use. Drop the single builtin DTB and let the boards using it pass the correct one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: NETX: remove architectureSascha Hauer2019-09-231-5/+0
|/ | | | | | | NETX support has been removed from the Kernel, so there's no point in supporting it in barebox any longer. Remove the architecture. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/qemu'Sascha Hauer2019-09-121-0/+18
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| * ARM: Add generic device tree 2nd stage supportSascha Hauer2019-08-191-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for building a barebox image that boots with the Linux ARM Kernel booting convention. Support for this image can be enabled in Kconfig. It picks up a device tree passed in r2. This new image helps for example with qemu. It can be started with: qemu-system-aarch64 -m 2G -M virt -kernel images/barebox-dt-2nd.img -cpu cortex-a57 -serial stdio or: qemu-system-arm -m 1G -M sabrelite -kernel images/barebox-dt-2nd.img -nographic -dtb arch/arm/dts/imx6q-sabrelite.dtb Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Kconfig: create Kconfig symbol for ARCH_HAS_DATA_ABORT_MASKAhmad Fatoum2019-08-301-0/+1
| | | | | | | | | | | | | | | | Other arch-specific features are exposed in Kconfig too, so do here likewise. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Kconfig: create Kconfig symbol for ARCH_HAS_STACK_DUMPAhmad Fatoum2019-08-301-0/+1
|/ | | | | | | | Other arch-specific features are exposed in Kconfig too, so do here likewise. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: fix some misnomers/typosAhmad Fatoum2019-07-151-1/+1
| | | | | | | | | The arch was renamed to stm32mp, so it doesn't look out of place when the stm32mp2 is released. Fix spotted comments/labels with the old name. While at it, fix a typo about the SoC name on the DK2 board. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pinctrl: add driver for STM32 GPIO and pin multiplexerAhmad Fatoum2019-06-201-0/+1
| | | | | | | | | | | | | This adds driver support for the 12 GPIO banks on the STM32MP157. As they are accessible to both the Cortex-A cores as well as the Cortex-M core, modifications to these are protected by a hardware spinlock and clocks are enabled/disabled as required. All register fiddling done by the driver is collected in <soc/stm32/gpio.h>, so future PBL code may make use of it as well to chainload barebox proper. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp1: rename to stm32mpAhmad Fatoum2019-06-131-2/+2
| | | | | | | | | | | | Serial and clk driver both depend on CONFIG_ARCH_STM32MP1, so either the Kconfig symbol or their depend needs to change. Patches posted by the vendor to Linux, U-Boot and their BSP Yocto-Layer speak of a STM32MP-Family of which the STM32MP1 is the first series, thus rename the arch by dropping the 1. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: factor out of_psci_fixup() to separate fileSascha Hauer2019-05-131-0/+4
| | | | | | | | | of_psci_fixup() can be used by code which doesn't use the barebox psci implementation, but provides its own PSCI compatible firmware. Factor it out to a separate file to compile it independently of the barebox PSCI implementation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32'Sascha Hauer2019-04-091-0/+11
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| * ARM: Add initial STM32MP1 supportSascha Hauer2019-03-131-0/+11
| | | | | | | | | | | | | | | | | | | | | | This adds initial STMicroelectronics MP1 support along with support for the DK2 devel board. Only very basic support: - UART - SDRAM memory base/size - No 1st stage support Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2019-04-091-26/+26
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| * | treewide: surround Kconfig file paths with double quotesMasahiro Yamada2019-03-211-25/+25
| |/ | | | | | | | | | | | | | | | | Based on Linux commit 8636a1f9677db4f883f29a072f401303acfc2edd This will be needed when you sync Kconfig with Linux 5.0 or later. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: Add Layerscape clk supportSascha Hauer2019-03-131-0/+3
| | | | | | | | | | | | | | | | | | | | This adds support for the clock controller found on Layerscape SoCs. This is mostly an adoption of the corresponding Linux driver. This is tested on the LS1046a SoC. Other ARM based Layerscape SoCs should work aswell, support for the PowerPC based SoCs has been removed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Add basic Layerscape supportSascha Hauer2019-03-131-0/+7
|/ | | | | | | | | | This adds basic Layerscape support: - Makefile/Kconfig - Register maps - errata workarounds Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware-zynqmp: port from linuxThomas Haemmerle2019-02-271-0/+1
| | | | | | | Port Xilinx Zynq MPSoC Firmware layer driver from linux. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zynqmp: select macb driverThomas Haemmerle2019-01-301-0/+1
| | | | | | | macb supports Xilinx ZynqMP GEM, so select HAS_MACB by default. Signed-off-by: Thomas Haemmerle <thomas.haemmerle1988@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zynqmp: add support for Xilinx ZCU104 boardMichael Tretter2018-12-101-0/+14
| | | | | | | | | | | | | | Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP) and the Xilinx ZCU104 board. Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL) already took care of initializing the RAM. Also for debug_ll, the UART is expected to be already setup correctly. Thus, you have to add the Barebox binary to a boot image as described in "Chapter 11: Boot and Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual". Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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