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We now have second stage support for running from sdmmc0 and sdmmc1.
Add a barebox environment and update handler for the two SD cards.
As fall back, we use the environment in the QSPI flash as before as this
is soldered to the SoM and is always available.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The BootROM passes us information about the boot medium in r4 and we
already use that in first stage and pass it along to second stage
PBL already. To make use of it, we need to pass it to barebox proper, do
this by writing it in the last 4 bytes of the SRAM. As second stage
always run in DRAM, this is safe to do.
We could also write to SRAM directly from first stage, but at91bootstrap
passes info in r4 as well for the sama5d3 boards, so we do it likewise
to maintain compatibility.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We hard code memory size at three places:
- In the configuration we use to initialize the DDRAM controller
- In the minimal available size passed from PBL to barebox proper
- In the device tree memory node override
Remove the two latter ones and replace them with code that reads the
size back from controller.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The BootROM constrains us to a 64K big first stage bootloader. Add a PBL
entry point for a xload barebox that sets up the minimum necessary to
load a FAT32 barebox.bin from the SD-Card.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The sama5d2 can be fused for one of 9 preset UART iosets. This is then
used by the BootROM for printing the `RomBOOT' header and for the XMODEM
protocol implemented by the SAM-BA monitor. Add two new sama5d2 specific
helpers:
- sama5d2_dbgu_setup_ll for setting up the port with only pinmux and
master clock as arguments
- sama5d2_resetup_uart_console for resetup of the uart console with
same pinmux used by the ROM code
The default value, when unfused, is UART_1_IOSET_1 (RX@PD2, TX@PD3),
which are the same ones used on the two sama5d2 board supported so far.
With this change, the DEBUG_LL baudrate is also no longer fixed at 115200,
but instead comes from the CONFIG_BAUDRATE symbol.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Stack is always set up to end of SRAM before PBL, either by ROM code or
by first stage bootloader, be it at91bootstrap or barebox in a later
commit, so no need to change the stack pointer again.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Port over the low level initialization for sama5d2 SoCs from
at91bootstrap.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The peripheral addresses should be always cast with IOMEM() anyway, so do
this directly in the header to make user code less verbose.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We need to branch out as soon as possible after setting up the stack.
Do this and thereby avoid an access violation we now run into using
OSELAS.Toolchain-2019.09.1.
Fixes: 8bfb1852cf6a ("ARM: at91: add basic sama5d2-som1-ek1 support")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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In ARM, stack decrements before storing values, so decrementing a number
from the stack base is unnecessary. Existing instances of this were
removed in 6b3dc4abd8 ("ARM: Cleanup stack offset cargo cult"), but the
sama5d27-som1 board was added later than that. Fix the cargo cult here
as well and while at it, turn a macro that doesn't need to be one
into a static inline function.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The ATSAMA5D27-SOM1-EK1 is Microchip's evaluation kit for the SAMA5D2
System in Packages (SiPs). The ATSAMA5D27C-D1G-CU SIP embeds 128 MB
of DDR2 DRAM and the SoM has a PMIC, QSPI flash and a 100Mbps PHY.
barebox already supports the sama5d2 clocks, GPIO/Pinctrl, QSPI
controller and Ethernet MAC. Most notable omission is the sama5d2
variant of the SDHCI, which differs from the MCI used by previous AT91
boards, but we kernel boot over the network works, so lets add the board
now and have the SDHCI follow later.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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