| Commit message (Collapse) | Author | Age | Files | Lines |
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Move defines to header file to make them reusable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When booting a Raspberry Pi, it is useful to extract bootargs from the
device tree that was created by the VideoCore firmware. These bootargs
contain for example settings for the framebuffer that the kernel needs
to properly set the video output.
This commit extracts the bootargs in the board initialization code and
saves them to the vc.bootargs global variable.
For example, a bootloader environment can then add the contents of this
variable to linux.bootargs.vc, which then gets included into the final
bootargs for the kernel using CONFIG_FLEXIBLE_BOOTARGS.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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On Raspberry Pi, VideoCore firmware creates a device tree that contains
information about peripherals that were initialized by VideoCore based
on settings in config.txt. Normally this device tree is passed to the
Linux kernel via a pointer in the r2 register. A bootloader needs to
pass this device tree to the kernel, or some peripherals will not work
correctly.
Since the VideoCore device tree is not compatible with barebox, we can't
just pass it to barebox_arm_entry() as the internal barebox device tree.
This commit makes the prebootloader code copy the device tree from
VideoCore into a scrap RAM area just above the area reserved for the
bootloader. Board initialization code in the bootloader proper then
copies it into a file /vc.dtb. The bootloader environment is then free
to pass this file to the kernel at boot (e.g. via bootm -o).
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Compute Module needs "no-sd" property on the MMC interface otherwise
mci-bcm2835 hangs on SD card probe.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The phyCORE-i.MX8M aka PCL-066 is a SoM containing a i.MX8M SoC.
phyCORE-i.MX8M:
- 1GB LPDDR4 RAM
- eMMC
- microSD
- Ethernet
Signed-off-by: Christian Hemp <christian.hemp@posteo.de>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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With this patch the two last lines are added to the output of the
following command:
$ ./scripts/bareboximd images/barebox-phytec-phycore-imx6dl-som-emmc-1gib.img
build: #15 Thu Feb 21 11:20:23 CET 2019
release: 2019.02.0-00235-gb03cf6f145ae-dirty
parameter: memsize=1024
of_compatible: phytec,imx6dl-pcm058-emmc fsl,imx6dl
model: Phytec phyCORE-i.MX6 DualLite/SOLO with eMMC
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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These functions are not meant to be a public interface, so they can well
be static. rpi_b_plus_init() was previously declared with a prototype,
which is no longer needed.
This fixes the following build warnings:
.../arch/arm/boards/raspberry-pi/rpi-common.c:124:6: warning: no previous prototype for 'rpi_add_led' [-Wmissing-prototypes]
void rpi_add_led(void)
^~~~~~~~~~~
.../arch/arm/boards/raspberry-pi/rpi-common.c:141:6: warning: no previous prototype for 'rpi_b_init' [-Wmissing-prototypes]
void rpi_b_init(void)
Signed-off-by: Roland Hieber <rhi@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Previously the clkdev_add_phybase was called on magic register values,
add defines which clarify the device for which the phybase clkdev is created.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The miniuart uses the core clock as the clock source. This clock is fixed by the
firmware to 250Mhz if enable_uart=1 is set in the config.txt file.
However a user could still choose to overclock the core frequency,
which would result in wrong baudrates computed by barebox.
Retrieve the core clock frequency from the firmware to allow all potential
firmware configurations to work with barebox.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We don't know if the firmware running on the raspberry pi is the same firmware
which is running on all bcm283x devices.
Therefore move the console clock initialization into the rpi-common.c board file.
A future commit will use this function to retrieve the miniuart clock from the
raspberry pi firmware.
No functional changes.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The PFC200 has a KSZ886x switch connected. Some of its registers need to
be initialized for proper ehternet support. Add the initialization code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Heinrich.Toews@wago.com
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arch/arm/boards/qemu-virt64/Kconfig is not used by build system,
so it can be removed.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Just a cleanup over barebox tree
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add support for the following ZII i.MX8MQ based boards:
- ZII i.MX8MQ RMB3
- ZII i.MX8MQ Zest
Most of the basic peripherals are supported by this patch. More
advanced features such as PCIe, display support, etc, are planned to
be added later.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We don't intend to ship any files in this directory, so there is no
risk of the directory getting too crowded over time. Drop the subdir
as this makes it easier for a outer build system to drop all the
needed firmwares into the correct directory.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Original patch from Uwe Kleine-König, I fixed the
review comments and the imxcfg file to use the udoo neo values.
I also tested the support on the udoo neo full board.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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As for tftp, make use of the initramfs if one is present on the SD card.
Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com>
Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since 5f99a8d40305 ("dts: VFxxx: Add aliases for ESDHC controllers"),
the SD card slot has a consistent name across all ZII Dev platforms,
including CFU1. They all use mmc1 instead of mci0 or mci1.
This allows us to completely drop the init scripts from the default
ZII VF610 Dev environment, and fix the boot/sd script.
Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com>
Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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"model" pointer is NULL if current board revision isn't in the list of known
boards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP)
and the Xilinx ZCU104 board.
Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL)
already took care of initializing the RAM. Also for debug_ll, the UART
is expected to be already setup correctly. Thus, you have to add the
Barebox binary to a boot image as described in "Chapter 11: Boot and
Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual".
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fix mistake in Makefile that prevented build of
of_init.o
With this fix smc shows up in iomem like this:
0xffffe400 - 0xffffe5ff (size 0x00000200) at91sam9-smc0
0xffffea00 - 0xffffebff (size 0x00000200) at91sam9-smc1
And we get access to the files from defaultenv provided by the board
Fixes: b467c262b5a7 (at91sam9263ek: enable DT support)
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This is a cumulative patch for the Digi ConnectCore CCMX51 SOM.
It includes:
- Switch board to devicetree probe.
- Add MMC update handler.
- Switch to multiimage support.
- Cleanup and optimize board code.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patch revises the bits for register MC13892_POWER_MISC.
- Added definition for one missing bit (0).
- Changed the name for bit 21 for accordance with the datasheet.
- Updated affected board that uses these definitions.
- Replaced spaces with tabs for the remaining bits.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This command allows to reset the network switch on the DEB,
clearing any DSA configuration, which may still be present from
a prior boot.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Some older pca100 boards were available with 64MB RAM. The chips
require a slightly different sdram controller initialization. Support
this by building bootloader images for both variants.
Signed-off-by: Florian Bäuerle <florian.baeuerle@allegion.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add bootchooser as primary boot source for NAND and eMMC.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds support for the AM3517 based WAGO pfc200 SPS.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Check for the correct hardware before reading the eeprom.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The socfpga xload images are limited to 64KiB. This doesn't fit if
multiple boards are selected. The reason is that we include huge
C files and arrays in the early init code which get compiled once
for each board. -ffunction-sections is without effect here since all
functions have the same name and hence we get the same function
multiple times in the same section.
To overcome this we surround all function names with a SECT() macro which
is used to add a board specific prefix to the section names. This way
-ffunction-sections can now do its work and discard unused functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The phyCORE-i.MX 6ULL now comes in a full featured (Y2 variant) and a
low cost (Y0 variant) version. The main difference for the barebox is
the missing second USB OTG port on the Y0 variant and the RAM configuration.
So to account for these differences the existing low cost version is
renamed and the full featured version added.
The results are following phyCORE-i.MX 6ULL modules:
phyCORE-i.MX 6ULL low cost:
- i.MX 6ULL Y0
- 256 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
phyCORE-i.MX 6ULL full featured:
- i.MX 6ULL Y2
- 512 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
- USB Host
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The way we assemble the multi images on ARM is rather complicated and
error prone. We currently cat the compressed barebox image behind the
PBL executable and need some magic to obtain the size of the payload and
also have to do tricks to reliably get a pointer to the compressed
image.
This patch switches over to compile the compressed payload into the PBL
image itself which has proven to work for the single PBL case and for
the ARM Linux Kernel aswell.
The goal is to unify the single PBL and the multi PBL cases together in
the future to get an easier startup path for ARM.
This patch has been tested on the i.MX53 QSB, i.MX53 Vincell, Beaglebone
black (both MLO and 2nd stage) and a Phytec phyFLEX i.MX6 board.
SoCFPGA Arria10 has also be changed slightly with this patch. We used to
generate a single image (barebox-socfpga-achilles.img) which was
used as xload image and full image. We now instead generate two images:
barebox-socfpga-achilles-xload.img and barebox-socfpga-achilles.img, the
former loaded by the ROM and the latter loaded by the xload image.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The max_load_size option makes sure that only the portion of the image
is loaded to SRAM that fits into it.
Note this does not cover the whole available SRAM area for all boards,
for the bigger SRAM areas only a part is chosen that is enough to fit
the initial loader in.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The PBL unnecessarily contains two dtb files when only one is needed. Be
a bit more smart and compile in only one.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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