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* arm64: disable PBL supportLucas Stach2017-01-091-0/+1
| | | | | | | PBL is another feature, which needs some love to work on ARM64. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm(64): move HAS_DMA and HAS_MODULES to CPU_32Lucas Stach2016-10-041-0/+2
| | | | | | | | We don't yet have an implementation for those two features on ARM64, so move them to a place where they are only selected for a 32bit barebox. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm64: select ARM_EXCEPTIONSLucas Stach2016-10-041-0/+1
| | | | | | | | | The current ARM64 lowlevel code needs the exception vector to set up all the ELs. Select ARM_EXCEPTIONS to make sure this is always present. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm64: add armv8 Kconfig entriesRaphael Poggi2016-07-061-1/+32
| | | | | Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: pxa: add pxa3xx architectureRobert Jarzmik2015-01-191-0/+6
| | | | | | | | | | | | | | | Add the pxa3xx architecture, for pxa300, pxa310 and pxa320 SoCs. This includes : - the registers - the cpu type - the reset source handling - a minimal set of clocks - pin control definitions In this last case, the big mfp-pxaxxx.h files were dropped, forcing board developers to use MFP_LPM_* macros cunningly. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Let MMU depend on !CPU_ARM946ESascha Hauer2014-11-281-1/+0
| | | | | | | CPU_ARM946E is selected by boards, so letting it depend on !MMU leads to broken dependencies. Let MMU depend on !CPU_ARM946E instead. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: add ARM946E-S CPU typeAntony Pavlov2014-07-291-0/+13
| | | | | | | | | | | | | | | | | | | ARM946E-S is used in the DIGIC family SoCs. ARM946E-S core supports ARMv5TE and has Cache & MPU. Linux kernel uses ARMv4 MPU cache routines for ARM946E-S core. E.g. see linux.git/boot/compressed/head.S: .word 0x41009400 @ ARM94x .word 0xff00ff00 W(b) __armv4_mpu_cache_on W(b) __armv4_mpu_cache_off W(b) __armv4_mpu_cache_flush So select CPU_32v4T for ARM946E-S despite of ARMv5TE support. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: mvebu: add Feroceon CPU typeThomas Petazzoni2013-05-171-0/+8
| | | | | | | | | The Kirkwood Marvell SoC uses a Marvell-specific implementation of an ARMv5TE compatible ARM core, the Feroceon. This patch introduces a Kconfig option that allows to select this CPU type. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Cleanup Kconfig filesAlexander Shiyan2012-12-081-4/+3
| | | | | | | | | This patch provides a global cleanup barebox Kconfig files. This includes replacing spaces to tabs, formatting in accordance format, removing extraneous lines and spaces. No functional changes. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM1176: add supportCarlo Caione2012-10-211-0/+5
| | | | | Signed-off-by: Carlo Caione <carlo.caione@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Fix Kconfig link for Cirrus Logic EP9312 CPU.Alexander Shiyan2012-10-051-1/+1
| | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm/mach-pxa: Initial Intel/Marvell PXA supportMarc Kleine-Budde2011-12-051-0/+5
| | | | | | | | | | | | The core support was brought by Marc and Sascha. The cache choice was fixed by Luotao Fu. Some gpio and devices addons were provided by Robert. Signed-off-by: Luotao Fu <l.fu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM cache l2x0: depend on MMUSascha Hauer2011-08-011-1/+1
| | | | | | | l2x0 cache support does not work without MMU, so depend on it in Kconfig. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: support big/little endian switching in "bootX".Krzysztof Halasa2011-01-071-0/+9
| | | | | | | Currently implemented only in "bootz". Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: support big-endian processors.Krzysztof Halasa2010-12-211-0/+3
| | | | | Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* add l2x0 cache supportSascha Hauer2010-03-301-0/+8
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* add armv6 support to the konfig systemSascha Hauer2010-02-011-0/+8
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: add endian config supportJean-Christophe PLAGNIOL-VILLARD2009-11-031-0/+11
| | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: introduce CPU CONFIG from linuxJean-Christophe PLAGNIOL-VILLARD2009-11-031-0/+52
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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