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* ARM: cache-l2x0: Make use of IS_ALIGNED and ALIGN_DOWNAndrey Smirnov2018-08-221-6/+6
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: cache-l2x0: honour aux_val when determing way sizeSascha Hauer2017-04-211-4/+3
| | | | | | | | | | | | | | l2x0_init() allows to overwrite bits in the AUX_CTRL register using the aux_val/aux_mask arguments. On i.MX35 this is used to pass a correct AUX_CTRL value to overwrite bogus reset values for this register. To make this work we have to apply aux_val/aux_mask before using the AUX_CTRL value to determine the way size. This fixes: 3f7e890da7 ARM: l2x0: Implement L310 support Before this commit the way size was hardcoded to 8. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: l2x0: move outer cache flush on disable to userLucas Stach2015-10-131-2/+0
| | | | | | | | | | | | | There are systems like the Calxeda Highbank, which need to do SMC calls in order to access the secure L2C registers, which means they want to replace the outer cache disable function with their own. As the cache flush before entering the boot target is still needed and to avoid exposing L2C internals to the architectures move the flush before disable into the only current user. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: l2x0: correct indentationLucas Stach2015-10-131-2/+2
| | | | | | | This is a trivial commit. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: l2x0: Add some informational debug messagesSascha Hauer2015-08-081-0/+2
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: l2x0: Flush cache before disabling itSascha Hauer2015-08-081-1/+12
| | | | | | Otherwise entries may still be in the cache and never reach memory. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: l2x0: Implement L310 supportSascha Hauer2015-08-081-2/+31
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: cache-l2x0 update sync define with Linux 3.5Jean-Christophe PLAGNIOL-VILLARD2013-02-111-31/+1
| | | | | | | Drop copy in cache-l2x0 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* introduce io.hSascha Hauer2011-09-221-1/+1
| | | | | | | To allow for some generic io accessors introduce io.h and use this instead of asm/io.h throughout the tree. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* cache-l2x0: sparse fixesSascha Hauer2010-10-211-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* add l2x0 cache supportSascha Hauer2010-03-301-0/+183
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-14 12:15:27 +0000