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* ARM: vector_table: Fix creation of second level page tableSascha Hauer2016-08-261-1/+1
| | | | | | | | | | | | | | | | | The second level page tables can only start at a 1MiB section boundary, so instead of calling arm_create_pte() with the high vector address (which is 0xffff0000, not 1MiB aligned) we have to call it with 0xfff00000 to correctly create a second level page table. The old values broke SoCs which have peripherals in the upper 1MiB area, like for example the Atmel AT91RM9200. On these Socs we correctly created the vector page, but the pages around it did not have a 1:1 mapping anymore which led to unreachable peripherals. Fixes: f6b77fe9: ARM: Rework vector table setup Reported-by: Peter Kardos <kardos.peter.sk@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Peter Kardos <kardos.peter.sk@gmail.com>
* ARM: Rework vector table setupSascha Hauer2016-04-011-37/+127
| | | | | | | | | | | | | | | | | | | The current vector table setup has some shortcomings. First of all currently the case when the high vectors are inside SDRAM (that is, SDRAM reaches the end of the address space) is not supported. In this case we create a secondary page table for the section containing the vectors which gets overwritten by the general SDRAM secondary page table entries creation afterwards. On ARMv7 and later the exception table setup can be improved: Here the vector table address is configurable in the VBAR register. We can use this register to skip remapping the vector table. With this patch we first try to use the VBAR register before doing something else. Also, when we have to use the high vectors we first try a request_sdram_region to test if the vector table memory is already mapped. While at it sprinkle some comments into the code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mmu: Add VBAR setupAndrey Smirnov2016-01-111-0/+10
| | | | | | | | | Add code to make sure that normal vector exception table, when it is used due to unavailability of the high vector table, was not re-mapped from 0x0 via VBAR by someone else before us. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Fix bug in remap_rangeSascha Hauer2015-11-131-16/+22
| | | | | | | | | | | remap_range takes generic MAP_CACHED/MAP_UNCACHED flags which are then translated into the corresponding ARM specific bits. We call remap_range internally from dma_alloc_* aswell, but instead of passing the generic flags we pass the ARM specific bits. Fix this by creating an internal __remap_range function which takes the ARM specific bits and use it where appropriate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* rework remap_rangeSascha Hauer2015-11-031-13/+17
| | | | | | | | | | | | | | | | | | remap_range is for remapping regions with different cache attributes. It is implemented for ARM and PowerPC only, the other architectures only provide stubs. Currently the new cache attributes are passed in an architecture specific way and the attributes have to be retrieved by calls to mmu_get_pte_cached_flags() and mmu_get_pte_uncached_flags(). Make this simpler by providing architecture independent flags which can be directly passed to remap_range() Also provide a MAP_ARCH_DEFAULT flag and a arch_can_remap() function. The MAP_ARCH_DEFAULT defaults to whatever caching type the architecture has as default. the arch_can_remap() function returns true if the architecture can change the cache attributes, false otherwise. This allows the memtest code to better find out what it has to do. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MMU: fixed calculation of number of PTEsEnrico Scholz2015-09-211-1/+1
| | | | | | | | | | | | | barebox uses 4KiB pages so that number of PTEs is 'size >> 12', not 'size >> 10'. Thie 'size >> 10' limit is not an immediate problem because it allocates too much PTEs only which are not used. But it can overflow an integer multiplication ('i * PAGE_SIZE') which causes undefined behaviour with gcc5. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MMU: fixed dma_flush_range() callEnrico Scholz2015-09-211-1/+2
| | | | | | | dma_flush_range() expects an address as second argument, not a size. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/fb-imx-ipu-v3'Sascha Hauer2015-09-011-0/+20
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| * implement dma_alloc_writecombineSascha Hauer2015-08-071-0/+20
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: MMU: Fix order when flushing inner/outer cacheSascha Hauer2015-08-071-1/+1
|/ | | | | | | When flushing the cache L1 has to be flushed before L2, not the other way round. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/streaming-dma'Sascha Hauer2015-03-091-18/+37
|\ | | | | | | | | Conflicts: drivers/mci/dw_mmc.c
| * ARM: MMU: unexport cache maintenance functionsLucas Stach2015-03-061-21/+14
| | | | | | | | | | | | | | | | Those should only be used internally. All users should rather use the streaming DMA API, which does proper cache maintenance. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: implement streaming DMA opsLucas Stach2015-03-061-0/+24
| | | | | | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: change dma_alloc/free_coherent to match other architecturesLucas Stach2015-03-061-2/+4
| | | | | | | | | | | | | | | | | | As a lot drivers currently rely on the 1:1 virt->phys mapping on ARM we define DMA_ADDRESS_BROKEN to mark them. In order to use them on other architectures with a different mapping they need proper fixing. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/arm'Sascha Hauer2015-03-091-2/+0
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| * ARM: remove unused variableSascha Hauer2015-02-111-2/+0
| | | | | | | | | | | | arm_architecture is unused, remove it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm: virt_to_phys should take a volatile ptrLucas Stach2015-02-251-1/+1
|/ | | | | | | | So users can pass in device memory pointers without provoking warnings. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: delete useless and wrong commentsMasahiro Yamada2015-01-301-2/+0
| | | | | | | | These comments are wrong. Anyway, they do not carry useful information. Delete. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sizes.h: move include/sizes.h to include/linux/sizes.hMasahiro Yamada2015-01-081-1/+1
| | | | | | | | | | | | | | This file originates in Linux. Linux has it under include/linux/ directory since commit dccd2304cc90. Let's move it to the same place as well in barebox. This commit was generated by the following commands: find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:' git mv include/sizes.h include/linux/ Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mmu: flush ttb in map_io_sectionsLucas Stach2014-07-221-0/+1
| | | | | | | | We need to flush out the ttb in order to make the changes observable to the page walker. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MMU: Fix memory reaching to the end of address spaceSascha Hauer2014-03-181-1/+1
| | | | | | | | | For memory reaching the end of the address space phys + bank->size overflows to 0. Fix this by right shifting phys and bank->size before adding them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Sean Cross <xobs@kosagi.com>
* ARM: MMU: Add some debugging aids and hintsSascha Hauer2014-03-171-2/+55
| | | | | | | | | | | | | - If we have no memory registered in mmu_init() it's a critical bug. panic in this case. - If we do not have a ttb when dma_alloc_coherent or remap_range is called it's also a critical bug. Panic in this case. - if find_pte is called with an address outside our memory banks dump the memory banks and the address to give more clue what went wrong. Also add some hints what might went wrong to the code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: mmu: be more verbose if ttb setup failsJan Luebbe2013-10-061-1/+1
| | | | | Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mmu: Use PAGE_ALIGN in dma_free_coherentJan Weitzel2013-04-271-3/+4
| | | | | | | | We PAGE_ALIGN the size in dma_alloc_coherent so do it also when free the memory. Use PAGE_SIZE instead of magic numbers. Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARN: fixup vector addresses for relocatable binariesSascha Hauer2013-03-071-0/+2
| | | | | | | With relocatable binaries the vector addresses cannot be supplied by the linker. This adds support for fixing them up during runtime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: move outercase to cpu.c as some SoC as the ux500 always need to flush ↵Jean-Christophe PLAGNIOL-VILLARD2013-02-111-15/+0
| | | | | | | the l2x0 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mmu: Clear unpredictable bits for translation tableAlexander Shiyan2013-02-111-0/+3
| | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM mmu: pickup already enabled mmuSascha Hauer2013-02-041-1/+8
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2013-02-041-15/+28
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| * arm-mmu: switch pte flags vars to lower caseAlexander Aring2013-01-251-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | Old cache/uncache pte flags were declared as defines. Since these flags are determine at runtime they are static variables. This patch switch the naming style of these variables to lower case which is typically used for variables. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * arm-mmu: move PAGE_ALIGN macro to common.hAlexander Aring2013-01-181-2/+0
| | | | | | | | | | | | | | | | | | | | PAGE_ALIGN macro is needed to align addresses to page boundaries. Move this macro to another PAGE_* defines. Commands which uses remap_range function needs this macro. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * remap_range: make function 'remap_range' globalAlexander Aring2013-01-181-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | Change function remap_range in arm architecture to make it global accessable. For example command 'memtest' can change pte flags to enable or disable cache. Add dummy function for others architectures that doesn't have mmu or pte support. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM mmu: Use pr_debugSascha Hauer2013-01-271-3/+24
|/ | | | | | Also, specify a pr_fmt and add missing GPL header. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm-mmu: remove semicolon in arm mmu.cAlexander Aring2013-01-141-1/+1
| | | | | | | Remove semicolon in PAGE_ALIGN macro. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Support multiple ARM architecturesSascha Hauer2012-10-131-7/+21
| | | | | | | The different ARM architectures need different cache functions. This patch makes them selectable during runtime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM mmu: use xmemalignSascha Hauer2012-09-161-1/+1
| | | | | | So we do not silently fail. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM MMU: call __mmu_cache_* as regular C functionsSascha Hauer2012-08-131-19/+6
| | | | | | | | Now that __mmu_cache_* restore the registers they can be called as regular C functions. Create a header file for them and use C functions rather than inline assembly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM mmu: flush page tables in arm_mmu_remap_sdram()Sascha Hauer2012-07-031-1/+4
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM mmu: don't use CONFIG_MMU to disable mmu code, there are static inline ↵Marc Kleine-Budde2012-06-301-4/+0
| | | | | | | versions Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: move exception vectors away from start of binarySascha Hauer2012-02-281-2/+2
| | | | | | | | | | | | | | | | Traditionally U-Boot and barebox have the exception vectors at the start of the binary. There is no real reason in doing so, because in the majority of cases this data will not be at 0x0 where it could be used as vectors directly anyway. This patch puts the vectors into a separate linker section and defines an head function which is placed at the start of the image instead. Putting this in a separate function also has the advantage that it can be placed at the start of images which require an additional header like several Freescale i.MX images. As the head function contains the barebox arm magic those images can now also be detected as barebox images. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'next'Sascha Hauer2012-01-051-0/+12
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| * arch/arm: mmu: add map_io_range()Robert Jarzmik2011-12-211-0/+12
| | | | | | | | | | | | | | | | | | Add a function to remap an IO range into a virtual addresses range. This is particulary usefull for the few devices mapped at physical address 0, as the MTD boot devices. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mark 'lr' as clobbered by inline assemblerEnrico Scholz2012-01-021-3/+3
|/ | | | | | | | When executing 'bl' in inline assembler, the 'lr' register must be marked as clobbered too. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: trivial renaming create_sectionsRobert Jarzmik2011-11-271-3/+3
| | | | | | | | | | Rename create_section into create_sections, as the function is used to create multiple sections, and in particular it creates the 4096 sections of 1MBytes to have a 1:1 flat mapping of the 4GBytes address space. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: switch to generic memory banksSascha Hauer2011-09-231-11/+12
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM mmu: find second level descriptors by walking the page tableSascha Hauer2011-09-231-19/+20
| | | | | | | By doing this we can remove the ptes field in struct arm_memory which won't be present in a generic memory bank structure anymore. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM mmu: use high vectors if possibleSascha Hauer2011-08-071-6/+31
| | | | | | | Using high vectors allows us to map a faulting zero page to catch NULL pointer dereferences. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM mmu: fix arm_create_pteSascha Hauer2011-08-071-1/+1
| | | | | | | Each section is 1MiB, so we have to shift by 20 to get the ttb entry corresponding to a section. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM mmu: Fix arm_create_pteSascha Hauer2011-08-031-1/+3
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM boards: remove now unnecessary mmu callsSascha Hauer2011-08-031-1/+2
| | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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