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* ARM: uncompress.c: Add some debugging messagesSascha Hauer2015-01-051-0/+9
| | | | | | | | Now that we have printf support in the PBL we can use it right after setup_c(). Add some debug messages to the early PBL code to make it more clear what is happening there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: start.c: Add some debugging messagesSascha Hauer2015-01-051-0/+11
| | | | | | | | pr_debug can now be used right after setup_c(), so add some debug messages to the early startup code to make it a bit more clear what is happening there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Let MMU depend on !CPU_ARM946ESascha Hauer2014-11-281-1/+0
| | | | | | | CPU_ARM946E is selected by boards, so letting it depend on !MMU leads to broken dependencies. Let MMU depend on !CPU_ARM946E instead. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/marvell'Sascha Hauer2014-08-071-0/+1
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| * ARM: execute OF fixups earlySebastian Hesselbarth2014-07-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Device trees can be passed by primary boot loader or appended to barebox binary. Unfortunately, before probing devices from such a device tree, no fixup can be applied. Add a call to of_fix_tree() right before probing devices to catch some very early fixups. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/canon'Sascha Hauer2014-08-071-0/+13
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| * | ARM: add ARM946E-S CPU typeAntony Pavlov2014-07-291-0/+13
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM946E-S is used in the DIGIC family SoCs. ARM946E-S core supports ARMv5TE and has Cache & MPU. Linux kernel uses ARMv4 MPU cache routines for ARM946E-S core. E.g. see linux.git/boot/compressed/head.S: .word 0x41009400 @ ARM94x .word 0xff00ff00 W(b) __armv4_mpu_cache_on W(b) __armv4_mpu_cache_off W(b) __armv4_mpu_cache_flush So select CPU_32v4T for ARM946E-S despite of ARMv5TE support. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/arm'Sascha Hauer2014-08-071-3/+3
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| * ARM: Increase automatic malloc area spaceSascha Hauer2014-07-211-3/+3
| | | | | | | | | | | | | | | | | | This increases the malloc to half of the available memory in a bank. This helps with some usecases requiring a lot of memory. The other half is still available as scratch area and for putting the kernel binary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mmu: flush ttb in map_io_sectionsLucas Stach2014-07-221-0/+1
|/ | | | | | | | We need to flush out the ttb in order to make the changes observable to the page walker. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: uncompress.c: copy executable to SDRAM if necessarySascha Hauer2014-06-132-8/+21
| | | | | | | | | | | We used to relocate the executable to the current address. This does not work when the executable runs from a readonly location like for example NOR Flash. Test if we run from inside the available memory and if we do, relocate to the current address as before. Otherwise copy the executable to the start of memory and relocate to that address. While at it add some comments to the code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: remove address of the Free Software FoundationAntony Pavlov2014-06-113-9/+0
| | | | | | | | | | | | | | | | | | The FSF address has changed; The FSF site says that address is Free Software Foundation 51 Franklin Street, Fifth Floor Boston, MA 02110-1301 USA (see http://www.fsf.org/about/contact/) Instead of updating it each time the address changes, just drop it completely treewide. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* misc: upper-case some abbreviationsHolger Schurig2014-06-021-1/+1
| | | | | Signed-off-by: Holger Schurig <holgerschurig@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: Drop devicetree merge supportSascha Hauer2014-05-221-1/+1
| | | | | | | | | | | | I assume I am the only person knowing that barebox is able to merge devicetrees. This feature seems broken for a while now since trying to merge devicetress results in: unflatten: too many end nodes Remove this feature to save the complexity. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* commands: harmonize in-barebox documentationHolger Schurig2014-05-142-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does probably too much, but it's hard (and very cumbersome/time consuming) to break it out. What is does is this: * each command has one short description, e.g. "list MUX configuration" * made sure the short descriptions start lowercase * each command has one usage. That string contains just the options, e.g. "[-npn]". It's not part of the long help text. * that is, it doesn't say "[OPTIONS]" anymore, every usable option is listed by character in this (short) option string (the long description is in the long help text, as before) * help texts have been reworked, to make them - sometimes smaller - sometimes describe the options better - more often present themselves in a nicer format * all long help texts are now created with BUSYBOX_CMD_HELP_ macros, no more 'static const __maybe_unused char cmd_foobar_help[]' * made sure the long help texts starts uppercase * because cmdtp->name and cmdtp->opts together provide the new usage, all "Usage: foobar" texts have been removed from the long help texts * BUSYBOX_CMD_HELP_TEXT() provides the trailing newline by itself, this is nicer in the source code * BUSYBOX_CMD_HELP_OPT() provides the trailing newline by itself * made sure no line gets longer than 77 characters * delibertely renamed cmdtp->usage, so that we can get compile-time errors (e.g. in out-of-tree modules that use register_command() * the 'help' command can now always emit the usage, even without compiled long help texts * 'help -v' gives a list of commands with their short description, this is similar like the old "help" command before my patchset * 'help -a' gives out help of all commands Signed-off-by: Holger Schurig <holgerschurig@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* commands: group 'help' outputHolger Schurig2014-05-142-0/+2
| | | | | | | | | | | | | | | | | | | The old output of "help" was just producing a long list, that usually scrolled of the screen (even on a X11 terminal). This list is more compact, and also sorted by groups. The old output format (plus grouping) is now available with 'help -v'. Example: Information commands: ?, devinfo, help, iomem, meminfo, version Boot commands: boot, bootm, go, loadb, loads, loadx, loady, saves, uimage ... Signed-off-by: Holger Schurig <holgerschurig@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: change signature of barebox_arm_entryLucas Stach2014-05-053-22/+21
| | | | | | | | | | | Mostly to make it clear that boarddata needs to be something we can dereference. As this is a pretty invasive change, use the opportunity to make the signature 64bit safe. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MMU: Fix memory reaching to the end of address spaceSascha Hauer2014-03-181-1/+1
| | | | | | | | | For memory reaching the end of the address space phys + bank->size overflows to 0. Fix this by right shifting phys and bank->size before adding them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Sean Cross <xobs@kosagi.com>
* ARM: MMU: Add some debugging aids and hintsSascha Hauer2014-03-171-2/+55
| | | | | | | | | | | | | - If we have no memory registered in mmu_init() it's a critical bug. panic in this case. - If we do not have a ttb when dma_alloc_coherent or remap_range is called it's also a critical bug. Panic in this case. - if find_pte is called with an address outside our memory banks dump the memory banks and the address to give more clue what went wrong. Also add some hints what might went wrong to the code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* bugfix: don't rely on lr in arm_cpu_lowlevel_init张忠山2014-02-271-1/+2
| | | | | Signed-off-by: 张忠山 <zzs213@126.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2014-02-031-4/+0
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| * ARM: uncompress: Remove unused variableAlexander Shiyan2014-01-291-4/+0
| | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mode cpu_architecture() to common.cSascha Hauer2014-01-292-14/+14
| | | | | | | | | | | | | | It might be needed in pbl code, so move it to a file which is compiled in pbl mode. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Do not use BUG() in pbl codeSascha Hauer2014-01-291-1/+1
| | | | | | | | | | | | | | BUG() uses printf which is not available in pbl, so do not use it here. This becomes necessary when multiple CPU architectures are compiled in. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Pass armv7-a AFLAGS to cache-v7Sascha Hauer2014-01-291-0/+2
|/ | | | | | | | The cache-v7 code uses assembler instructions which do not exist on before v7, so explicitely pass armv7-a to this file to make the compiler happy. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Make multi images startup process simplerSascha Hauer2013-12-103-54/+6
| | | | | | | | | | | The multi image startup process used to have three binaries involved: - The lowlevel board code to initialize SDRAM - the uncompressor - the regular (compressed) barebox binary Drop the uncompressor and put the uncompress code into the lowlevel board code binary. This makes the startup process easier. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2013-12-061-0/+1
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| * treewide: Add missing includesSascha Hauer2013-11-081-0/+1
| | | | | | | | | | | | | | | | A lot of files rely on include/driver.h including include/of.h (and this including include/errno.h. include the files explicitly so we can eventually get rid of including of.h from driver.h Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: fix fdt inside valid memory checkSascha Hauer2013-11-261-1/+1
|/ | | | | | | We want to check whether boarddata contains a valid dtb if it's inside valid memory. This includes the base of SDRAM, so use '>=' instead of '>'. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: cache: do not crash when the MMU isn't yet setupAndre Heider2013-10-221-6/+12
| | | | | | | | | | | | | | | | | Drivers currently cannot implement explicit cache handling and rely on running the same code before and after mmu_initcall() without crashing. Depending on the chosen config options, the cache functions are not yet setup and using them early on ends in a null pointer dereference. The RPi's mailbox driver is such a case; it requires cache handling once the MMU is fully set up and yet the RPi setup needs to use the driver to get the memory size before mem_initcall() and hence mmu_initcall(). Fix this by checking the cache_fns pointer before dereferencing it. Signed-off-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: cache: restore cache functions from the PBLAndre Heider2013-10-221-1/+3
| | | | | | | | | | | When using CONFIG_MMU_EARLY combined with CONFIG_PBL_IMAGE, the barebox setup reuses the MMU setup from the PBL, but doesn't setup the cache functions. Set these up to guarantee proper early cache handing before mmu_initcall(). Signed-off-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: mmu: be more verbose if ttb setup failsJan Luebbe2013-10-061-1/+1
| | | | | Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: invalidate caches thoroughlySascha Hauer2013-09-213-4/+8
| | | | | | | | | | | | The data caches should be invalided once during startup. This should also be done when we do not have the MMU enabled in barebox because the Kernel does not invalidate the caches during start. To make this sure this patch enables the arm_early_mmu_cache_invalidate function even if MMU support is disabled. Additionally this patch adds calls to arm_early_mmu_cache_invalidate in start.c and uncompress.c. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/omap'Sascha Hauer2013-09-051-0/+33
|\ | | | | | | | | Conflicts: arch/arm/boards/pcm051/env/config
| * ARM: cpuinfo: display the core name and versionJan Luebbe2013-08-271-0/+33
| | | | | | | | | | Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Create an assembly arm_cpu_lowlevel_init functionSascha Hauer2013-08-072-0/+41
|/ | | | | | | To avoid the code duplication between the static inline C function and the assembly macro. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Add multi images supportSascha Hauer2013-07-013-1/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the make infrastructure to build multiple SoC or board specific images from a single barebox binary. The basic idea is that we no longer have a single pbl, but instead multiple pbls, one per image if necessary. Each pbl is defined by its entry function so that each pbl can do exactly what a given board needs. Additionally the pbls together with a self extracting barebox binary can be encapsulated in specific image formats. squashed in build fixes from Lucas Stach for make version >= 3.82: Split Multimage Makefile rule in explicit and implicit parts Fixes build with make version >=3.82 Frome the make 3.82 NEWS file: * WARNING: Backward-incompatibility! In previous versions of make it was acceptable to list one or more explicit targets followed by one or more pattern targets in the same rule and it worked "as expected". However, this was not documented as acceptable and if you listed any explicit targets AFTER the pattern targets, the entire rule would be mis-parsed. This release removes this ability completely: make will generate an error message if you mix explicit and pattern targets in the same rule. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Lucas Stach <dev@lynxeye.de>
* ARM: Allow to pass a devicetree via boarddataSascha Hauer2013-06-263-3/+41
| | | | | | | Addionally to having a builtin DTB provide the possibility for the board to provide a dtb via boarddata. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/marvell'Sascha Hauer2013-06-021-0/+8
|\ | | | | | | | | Conflicts: arch/arm/Makefile
| * arm: mvebu: add Feroceon CPU typeThomas Petazzoni2013-05-171-0/+8
| | | | | | | | | | | | | | | | | | The Kirkwood Marvell SoC uses a Marvell-specific implementation of an ARMv5TE compatible ARM core, the Feroceon. This patch introduces a Kconfig option that allows to select this CPU type. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2013-06-021-1/+1
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| * | treewide: Fix typo seperate -> separateSascha Hauer2013-05-211-1/+1
| |/ | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: invalidate data caches during early initSascha Hauer2013-05-233-0/+25
| | | | | | | | | | | | | | | | | | | | Some SoCs come up with invalid entries in the data cache. This can lead to memory corruption when we enable them later, so invalidate the caches early. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de>
* | ARM v7: added v7_mmu_cache_invalidate()Enrico Scholz2013-05-231-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At least the iMX6 boot rom seems to jump into barebox with a non invalidated d-cache which causes data corruption when v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides stack or other valid data. That's why the cache must be invalided for this processors explicitly (e.g. in barebox_arm_reset_vector()). Operation differs from flush only in one instruction so that patch modifies the existing v7_mmu_cache_flush() function slightly by adding an optional argument. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM v7: v7_mmu_cache_flush(): do not restore r0-r3 (minor optimization)Enrico Scholz2013-05-231-2/+2
| | | | | | | | | | | | | | | | Registers 'r0' till 'r3' are scratch registers and do not need to be restored. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM v7: fix mmu-off operationEnrico Scholz2013-05-171-25/+25
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although conclusions in 50d1b2de8ea0f3b8d89fe3a97ce64315996ed4cb "ARM v7: Fix register corruption in v7_mmu_cache_off" are correct, the implemented fix is not complete because the following failure can happen: 1. d-cache contains the cache line around 'sp' 2. v7_mmu_cache_off() disables cache 3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack 4. v7_mmu_cache_flush() flushes d-cache and can override stack written by step 3. 5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which might be random data now. Patch avoids step 3 which is easy because 'lr' is never modified by the function. By using the 'r12' scratch register instead of 'r10', the whole initial 'push' can be avoided. Patch moves also the 'DMB' operation so that it is executed after data has been pushed on stack. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mmu: Use PAGE_ALIGN in dma_free_coherentJan Weitzel2013-04-271-3/+4
| | | | | | | | We PAGE_ALIGN the size in dma_alloc_coherent so do it also when free the memory. Use PAGE_SIZE instead of magic numbers. Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/relocate'Sascha Hauer2013-04-049-43/+235
|\ | | | | | | | | Conflicts: arch/arm/lib/barebox.lds.S
| * ARM: Add relocatable binary supportSascha Hauer2013-03-075-4/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For making the same binary executable on different SoCs which have different DRAM addresses we have to be independent of the compile time link address. This patch adds relocatable binary support for the ARM architecture. With this two new functions are available. relocate_to_current_adr will fixup the binary to continue executing from the current position. relocate_to_adr will copy the binary to a given address, fixup the binary and continue executing from there. For the PBL and the real image relocatable support can be enabled independently. This is done to (hopefully) better cope with setups where the PBL runs from SRAM or ROM and the real binary does not. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARN: fixup vector addresses for relocatable binariesSascha Hauer2013-03-072-6/+51
| | | | | | | | | | | | | | With relocatable binaries the vector addresses cannot be supplied by the linker. This adds support for fixing them up during runtime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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