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* Merge branch 'for-next/misc'Sascha Hauer2014-02-031-4/+0
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| * ARM: uncompress: Remove unused variableAlexander Shiyan2014-01-291-4/+0
| | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mode cpu_architecture() to common.cSascha Hauer2014-01-292-14/+14
| | | | | | | | | | | | | | It might be needed in pbl code, so move it to a file which is compiled in pbl mode. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Do not use BUG() in pbl codeSascha Hauer2014-01-291-1/+1
| | | | | | | | | | | | | | BUG() uses printf which is not available in pbl, so do not use it here. This becomes necessary when multiple CPU architectures are compiled in. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Pass armv7-a AFLAGS to cache-v7Sascha Hauer2014-01-291-0/+2
|/ | | | | | | | The cache-v7 code uses assembler instructions which do not exist on before v7, so explicitely pass armv7-a to this file to make the compiler happy. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Make multi images startup process simplerSascha Hauer2013-12-103-54/+6
| | | | | | | | | | | The multi image startup process used to have three binaries involved: - The lowlevel board code to initialize SDRAM - the uncompressor - the regular (compressed) barebox binary Drop the uncompressor and put the uncompress code into the lowlevel board code binary. This makes the startup process easier. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2013-12-061-0/+1
|\ | | | | | | | | Conflicts: scripts/Makefile
| * treewide: Add missing includesSascha Hauer2013-11-081-0/+1
| | | | | | | | | | | | | | | | A lot of files rely on include/driver.h including include/of.h (and this including include/errno.h. include the files explicitly so we can eventually get rid of including of.h from driver.h Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: fix fdt inside valid memory checkSascha Hauer2013-11-261-1/+1
|/ | | | | | | We want to check whether boarddata contains a valid dtb if it's inside valid memory. This includes the base of SDRAM, so use '>=' instead of '>'. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: cache: do not crash when the MMU isn't yet setupAndre Heider2013-10-221-6/+12
| | | | | | | | | | | | | | | | | Drivers currently cannot implement explicit cache handling and rely on running the same code before and after mmu_initcall() without crashing. Depending on the chosen config options, the cache functions are not yet setup and using them early on ends in a null pointer dereference. The RPi's mailbox driver is such a case; it requires cache handling once the MMU is fully set up and yet the RPi setup needs to use the driver to get the memory size before mem_initcall() and hence mmu_initcall(). Fix this by checking the cache_fns pointer before dereferencing it. Signed-off-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: cache: restore cache functions from the PBLAndre Heider2013-10-221-1/+3
| | | | | | | | | | | When using CONFIG_MMU_EARLY combined with CONFIG_PBL_IMAGE, the barebox setup reuses the MMU setup from the PBL, but doesn't setup the cache functions. Set these up to guarantee proper early cache handing before mmu_initcall(). Signed-off-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: mmu: be more verbose if ttb setup failsJan Luebbe2013-10-061-1/+1
| | | | | Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: invalidate caches thoroughlySascha Hauer2013-09-213-4/+8
| | | | | | | | | | | | The data caches should be invalided once during startup. This should also be done when we do not have the MMU enabled in barebox because the Kernel does not invalidate the caches during start. To make this sure this patch enables the arm_early_mmu_cache_invalidate function even if MMU support is disabled. Additionally this patch adds calls to arm_early_mmu_cache_invalidate in start.c and uncompress.c. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/omap'Sascha Hauer2013-09-051-0/+33
|\ | | | | | | | | Conflicts: arch/arm/boards/pcm051/env/config
| * ARM: cpuinfo: display the core name and versionJan Luebbe2013-08-271-0/+33
| | | | | | | | | | Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Create an assembly arm_cpu_lowlevel_init functionSascha Hauer2013-08-072-0/+41
|/ | | | | | | To avoid the code duplication between the static inline C function and the assembly macro. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Add multi images supportSascha Hauer2013-07-013-1/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the make infrastructure to build multiple SoC or board specific images from a single barebox binary. The basic idea is that we no longer have a single pbl, but instead multiple pbls, one per image if necessary. Each pbl is defined by its entry function so that each pbl can do exactly what a given board needs. Additionally the pbls together with a self extracting barebox binary can be encapsulated in specific image formats. squashed in build fixes from Lucas Stach for make version >= 3.82: Split Multimage Makefile rule in explicit and implicit parts Fixes build with make version >=3.82 Frome the make 3.82 NEWS file: * WARNING: Backward-incompatibility! In previous versions of make it was acceptable to list one or more explicit targets followed by one or more pattern targets in the same rule and it worked "as expected". However, this was not documented as acceptable and if you listed any explicit targets AFTER the pattern targets, the entire rule would be mis-parsed. This release removes this ability completely: make will generate an error message if you mix explicit and pattern targets in the same rule. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Lucas Stach <dev@lynxeye.de>
* ARM: Allow to pass a devicetree via boarddataSascha Hauer2013-06-263-3/+41
| | | | | | | Addionally to having a builtin DTB provide the possibility for the board to provide a dtb via boarddata. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/marvell'Sascha Hauer2013-06-021-0/+8
|\ | | | | | | | | Conflicts: arch/arm/Makefile
| * arm: mvebu: add Feroceon CPU typeThomas Petazzoni2013-05-171-0/+8
| | | | | | | | | | | | | | | | | | The Kirkwood Marvell SoC uses a Marvell-specific implementation of an ARMv5TE compatible ARM core, the Feroceon. This patch introduces a Kconfig option that allows to select this CPU type. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2013-06-021-1/+1
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| * | treewide: Fix typo seperate -> separateSascha Hauer2013-05-211-1/+1
| |/ | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: invalidate data caches during early initSascha Hauer2013-05-233-0/+25
| | | | | | | | | | | | | | | | | | | | Some SoCs come up with invalid entries in the data cache. This can lead to memory corruption when we enable them later, so invalidate the caches early. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de>
* | ARM v7: added v7_mmu_cache_invalidate()Enrico Scholz2013-05-231-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At least the iMX6 boot rom seems to jump into barebox with a non invalidated d-cache which causes data corruption when v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides stack or other valid data. That's why the cache must be invalided for this processors explicitly (e.g. in barebox_arm_reset_vector()). Operation differs from flush only in one instruction so that patch modifies the existing v7_mmu_cache_flush() function slightly by adding an optional argument. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM v7: v7_mmu_cache_flush(): do not restore r0-r3 (minor optimization)Enrico Scholz2013-05-231-2/+2
| | | | | | | | | | | | | | | | Registers 'r0' till 'r3' are scratch registers and do not need to be restored. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM v7: fix mmu-off operationEnrico Scholz2013-05-171-25/+25
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although conclusions in 50d1b2de8ea0f3b8d89fe3a97ce64315996ed4cb "ARM v7: Fix register corruption in v7_mmu_cache_off" are correct, the implemented fix is not complete because the following failure can happen: 1. d-cache contains the cache line around 'sp' 2. v7_mmu_cache_off() disables cache 3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack 4. v7_mmu_cache_flush() flushes d-cache and can override stack written by step 3. 5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which might be random data now. Patch avoids step 3 which is easy because 'lr' is never modified by the function. By using the 'r12' scratch register instead of 'r10', the whole initial 'push' can be avoided. Patch moves also the 'DMB' operation so that it is executed after data has been pushed on stack. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mmu: Use PAGE_ALIGN in dma_free_coherentJan Weitzel2013-04-271-3/+4
| | | | | | | | We PAGE_ALIGN the size in dma_alloc_coherent so do it also when free the memory. Use PAGE_SIZE instead of magic numbers. Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/relocate'Sascha Hauer2013-04-049-43/+235
|\ | | | | | | | | Conflicts: arch/arm/lib/barebox.lds.S
| * ARM: Add relocatable binary supportSascha Hauer2013-03-075-4/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For making the same binary executable on different SoCs which have different DRAM addresses we have to be independent of the compile time link address. This patch adds relocatable binary support for the ARM architecture. With this two new functions are available. relocate_to_current_adr will fixup the binary to continue executing from the current position. relocate_to_adr will copy the binary to a given address, fixup the binary and continue executing from there. For the PBL and the real image relocatable support can be enabled independently. This is done to (hopefully) better cope with setups where the PBL runs from SRAM or ROM and the real binary does not. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARN: fixup vector addresses for relocatable binariesSascha Hauer2013-03-072-6/+51
| | | | | | | | | | | | | | With relocatable binaries the vector addresses cannot be supplied by the linker. This adds support for fixing them up during runtime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: add early mmu cache flush function and use it in setup_cSascha Hauer2013-03-042-0/+36
| | | | | | | | | | | | | | | | Since recently with MMU_EARLY support it may happen that setup_c runs with data caches enabled, so we have to make sure the caches are flushed before we jump to the new binary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: make cpu architecture detection available as static inline functionSascha Hauer2013-03-041-33/+1
| | | | | | | | | | | | | | | | | | When we have multi cpu support compiled in we need the cpu architecture early so that we can pick the correct cacheflush function. Make it available as static inline function and add a comment above it that this function normally should not be used. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/oftree'Sascha Hauer2013-04-042-0/+42
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| * | ARM: Initial dts supportSascha Hauer2013-03-122-0/+42
| |/ | | | | | | | | | | | | | | - Add rules to generate dtb files in arch/arm/dts/ - add an initcall which unflattens and probes the internal devicetree - Add skeleton devicetree Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / ARM: Add missing barebox_arm_boarddata functionSascha Hauer2013-03-101-0/+10
|/ | | | | | | | The comment above barebox_arm_entry promises to preserve the boarddata variable passed to it which can then later get back with barebox_arm_boarddata(). This function was missing so far, add it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: move outercase to cpu.c as some SoC as the ux500 always need to flush ↵Jean-Christophe PLAGNIOL-VILLARD2013-02-113-17/+26
| | | | | | | the l2x0 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: cache-l2x0 update sync define with Linux 3.5Jean-Christophe PLAGNIOL-VILLARD2013-02-111-31/+1
| | | | | | | Drop copy in cache-l2x0 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mmu: Clear unpredictable bits for translation tableAlexander Shiyan2013-02-111-0/+3
| | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: rename reset and common_reset to barebox_arm_reset_vector and ↵Jean-Christophe PLAGNIOL-VILLARD2013-02-081-1/+1
| | | | | | | | | arm_cpu_lowlevel_init reset is confusing with the cpu reset and impossible to grep Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM pbl: inline decompress functionSascha Hauer2013-02-041-8/+3
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Automatically determine malloc sizeSascha Hauer2013-02-041-0/+28
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Enable mmu earlySascha Hauer2013-02-042-1/+19
| | | | | | | | | This optionally enabled the MMU in the PBL or during early startup for the non PBL case. The regular MMU init code will pickup the already enabled MMU later. This might complicate debugging early code, so this has been made optional. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Factor out early mmu codeSascha Hauer2013-02-044-74/+61
| | | | | | | | | Move early mmu code to a separate file so that it can be used from the pbl and the regular image. Disabling the mmu can be dropped since the regular mmu code is now able to pickup an enabled mmu. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM mmu: pickup already enabled mmuSascha Hauer2013-02-041-1/+8
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM pbl: Use dynamic parameters for early malloc spaceSascha Hauer2013-02-041-4/+7
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Setup stack at end of SDRAMSascha Hauer2013-02-043-4/+30
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM start: pickup parameters from pblSascha Hauer2013-02-041-21/+23
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM start-pbl: call uncompressed binary with argumentsSascha Hauer2013-02-041-9/+9
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM start-pbl: make board_init_lowlevel_return staticSascha Hauer2013-02-041-9/+5
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: remove now unused MACH_[HAS|DO]_LOWLEVEL_INITSascha Hauer2013-02-042-24/+0
| | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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