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* ARM: execute DMB before trying to flush cacheLucas Stach2017-03-031-0/+1
| | | | | | | | | | The CPU write buffer needs to be coherent with the cache, otherwise we might flush stale entries with the actual data stuck in the cache. This is really important on newer CPU core with bigger write buffers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: correctly identify ARMv6 K/ZLucas Stach2017-03-031-0/+8
| | | | | | | | | | The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other parts (including the cache handling) is still at v6. As we don't make use of the more advanced features of the v7 MMU in Barebox, it's okay to just override this to properly identify the CPU as ARMv6. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2017-02-135-0/+813
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| * ARM: i.MX7: Add PSCI supportSascha Hauer2017-02-131-0/+13
| | | | | | | | | | | | | | This adds the SoC specific PSCI bits for i.MX7. Based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add PSCI supportSascha Hauer2017-02-134-0/+734
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains the barebox implementation for the ARM "Power State Coordination Interface" (PSCI). The interface is aimed at the generalization of code in the following power management scenarios: * Core idle management. * Dynamic addition and removal of cores, and secondary core boot. * big.LITTLE migration. * System shutdown and reset. In practice, all that's currently implemented is a way to enable the secondary core one some SoCs. With PSCI the Kernel is either started in nonsecure or in Hypervisor mode and PSCI is used to apply power to the secondary cores. The start mode is passed in the global.bootm.secure_state variable. This enum can contain "secure" (Kernel is started in secure mode, means no PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available) or "hyp" (Kernel is started in hyp mode, meaning it can support virtualization). We currently only support putting the secure monitor code into SDRAM, which means we always steal some amount of memory from the Kernel. To keep things simple for now we simply keep the whole barebox binary in memory The PSCI support has been tested on i.MX7 only so far. The only supported operations are CPU_ON and CPU_OFF. The PSCI and secure monitor code is based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add smc call supportSascha Hauer2017-02-082-0/+66
| | | | | | | | | | | | Taken from the Kernel: A wrapper to make a smc call from C. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: Fix image size calculationSascha Hauer2017-02-081-0/+3
| | | | | | | | | | | | | | | | | | | | In barebox_non_pbl_start() we do not run at the address we are linked at, so we must read linker variables using ld_var(). Since ld_var() current is not available on arm64 we create two zero sized arrays, one at the begin of the image and one at the end. The difference between both is the image size we are looking for. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: Fix boarddata allocationSascha Hauer2017-02-061-1/+1
|/ | | | | | | | | It's essential that we always pass the same size value to arm_mem_barebox_image(), otherwise the result will be inconsistent. Pass arm_barebox_size instead of barebox_image_size as the latter does not contain the max bss segment size. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Fix a bug in stack's "top" initializationAndrey Smirnov2017-01-092-2/+2
| | | | | | | | | | | | | | | | | | | Code-paths responsible for initializing CPU's stack pointer and variable used in stack memory resource reservation got out of sync which resulted in actual stack being 64K off from what "stack" struct resource registered by arm_request_stack() thought it was. At least one issue resulting from that can be easily triggered by running: memtest -t This commit unifies the aforementioned code to a certain degree which solves the problem and hopefuly makes it less likely to become an issue again. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm64: disable PBL supportLucas Stach2017-01-091-0/+1
| | | | | | | PBL is another feature, which needs some love to work on ARM64. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/arm'Sascha Hauer2016-10-103-8/+11
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| * ARM: Fix calling of arm_mem_barebox_image()Sascha Hauer2016-09-153-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm_mem_barebox_image() is used to pick a suitable place where to put the final image to. This is called from both the PBL uncompression code and also from the final image. To make it work properly it is crucial that it's called with the same arguments both times. Currently it is called with the wrong image size from the PBL uncompression code. The size passed to arm_mem_barebox_image() has to be the size of the whole uncompressed image including the BSS segment size. The PBL code calls it with the compressed image size instead and without the BSS segment. This patch fixes this by reading the uncompressed image size from the compressed binary (the uncompressed size is appended to the end of the compressed binary by our compression wrappers). The size of the BSS segment is unknown though by the PBL uncompression code, so we introduce a maximum BSS size which is used instead. The code before this patch worked by accident because the base address of the final image was aligned down to a 1MiB boundary. The alignment was sufficient already to make enough space. This breaks though when the uncompressed image including BSS becomes bigger than 1MiB while the compressed image is smaller. Fixes: 65071bd0: arm: Clarify memory layout calculation Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm64: include correct setupc file in ARM64 PBLLucas Stach2016-10-041-1/+3
| | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm(64): move HAS_DMA and HAS_MODULES to CPU_32Lucas Stach2016-10-041-0/+2
| | | | | | | | | | | | | | | | We don't yet have an implementation for those two features on ARM64, so move them to a place where they are only selected for a 32bit barebox. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm64: select ARM_EXCEPTIONSLucas Stach2016-10-041-0/+1
|/ | | | | | | | | The current ARM64 lowlevel code needs the exception vector to set up all the ELs. Select ARM_EXCEPTIONS to make sure this is always present. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of_unflatten_dtb(): Check return value with IS_ERRAndrey Smirnov2016-09-051-1/+1
| | | | | | | | Of_unflatten_dtb returns a ERR_PTR value so checking it against NULL is incorrect. Fix it in all of the places where this was happening. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: vector_table: Fix creation of second level page tableSascha Hauer2016-08-261-1/+1
| | | | | | | | | | | | | | | | | The second level page tables can only start at a 1MiB section boundary, so instead of calling arm_create_pte() with the high vector address (which is 0xffff0000, not 1MiB aligned) we have to call it with 0xfff00000 to correctly create a second level page table. The old values broke SoCs which have peripherals in the upper 1MiB area, like for example the Atmel AT91RM9200. On these Socs we correctly created the vector page, but the pages around it did not have a 1:1 mapping anymore which led to unreachable peripherals. Fixes: f6b77fe9: ARM: Rework vector table setup Reported-by: Peter Kardos <kardos.peter.sk@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Peter Kardos <kardos.peter.sk@gmail.com>
* Merge branch 'for-next/arm64'Sascha Hauer2016-07-1112-10/+920
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| * arm: cpu: add basic arm64 mmu supportRaphael Poggi2016-07-064-2/+389
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds basic mmu support, ie: - DMA cache handling is not supported - Remapping memory region also The current mmu setting is: - 4KB granularity - 3 level lookup (skipping L0) - 33 bits per VA This is based on coreboot and u-boot mmu configuration. Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * arm: cpu: disable code portion in armv8 caseRaphael Poggi2016-07-061-0/+5
| | | | | | | | | | | | | | | | Enclosed by #if directive OMAP specific code and mmu_disable (ARMv8 code will implemented it somewhere else). Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * arm: cpu: cpuinfo: add armv8 supportRaphael Poggi2016-07-061-4/+54
| | | | | | | | | | Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * arm: cpu: add arm64 specific codeRaphael Poggi2016-07-067-4/+441
| | | | | | | | | | | | | | | | | | | | This patch adds arm64 specific codes, which are: - exception support - cache support - rework Makefile to support arm64 Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * arm64: add armv8 Kconfig entriesRaphael Poggi2016-07-061-1/+32
| | | | | | | | | | Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: drop unnecessary variableSascha Hauer2016-06-201-5/+2
| | | | | | | | | | | | | | | | No need anymore to store arm_head_bottom globally as it's only used in barebox_non_pbl_start(). Also rename the variable to malloc_end which is more meaningful. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: simplify board_data sdram allocationSascha Hauer2016-06-201-5/+5
| | | | | | | | | | | | | | | | We already have a pointer for barebox_boarddata, so use it to request the corresponding SDRAM region instead of calculating it again. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: do not change barebox_boarddataSascha Hauer2016-06-201-2/+6
|/ | | | | | | | barebox_boarddata should stay the original boarddata and not be modified. Keep a local pointer in barebox_arm_boot_dtb() instead. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Rework vector table setupSascha Hauer2016-04-011-37/+127
| | | | | | | | | | | | | | | | | | | The current vector table setup has some shortcomings. First of all currently the case when the high vectors are inside SDRAM (that is, SDRAM reaches the end of the address space) is not supported. In this case we create a secondary page table for the section containing the vectors which gets overwritten by the general SDRAM secondary page table entries creation afterwards. On ARMv7 and later the exception table setup can be improved: Here the vector table address is configurable in the VBAR register. We can use this register to skip remapping the vector table. With this patch we first try to use the VBAR register before doing something else. Also, when we have to use the high vectors we first try a request_sdram_region to test if the vector table memory is already mapped. While at it sprinkle some comments into the code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Do not use last 64KiB of address space for bareboxSascha Hauer2016-04-011-1/+2
| | | | | | | | The last 64KiB of address space may be used for the vector table at 0xffff0000, so we cannot use it for barebox. The easiest way to archieve this is to never use the last 64KiB of memory. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: start: Fix wrong format specifierSascha Hauer2016-04-011-1/+1
| | | | | | Print a hex number after 0x, not a decimal number. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: pbl-multi: Fix SDRAM at end of address spaceSascha Hauer2016-04-011-1/+1
| | | | | | | | | When SDRAM reaches to the end of the address space the comparison membase + memsize evaluates to 0, so pc - membase < memsize can never be true. Fix this by substracting membase on both sides of the comparison. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm/cpu/lowlevel: fix: possible processor mode changeAlexander Kurz2016-03-041-1/+3
| | | | | | | | | | | This is a re-application of fix 17644b55. arm_cpu_lowlevel_init() will set the processor mode to 0x13 (supervisor). When this function is entered via a different processor mode, register banking will happen to lr (r14), resulting in an invalid return address. This fix will preserve the return address manually. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/pstore'Sascha Hauer2016-01-113-47/+69
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| * arm: Add RAMOOPS memory areaMarkus Pargmann2015-12-101-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | RAMOOPS is a driver that uses a reserved static memory region to store the data from the last panic or boot. This helps to debug crashes at the next boot while preserving the boot messages. To guarantee a memory area that is not altered by barebox or the kernel, this area is located at the end of the RAM right after barebox and before the STACK. This ensures that changing barebox sizes do not interfere with RAMOOPS. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * arm: start: Add visible sdram region for barebox board dataMarkus Pargmann2015-12-101-1/+18
| | | | | | | | | | | | | | | | | | This helps to understand and find problems with the memory layout of barebox. It adds another entry for the board data that barebox allocated. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * arm: Clarify memory layout calculationMarkus Pargmann2015-12-103-47/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory calculations used are all hardcoded into three different files, start-pbl.c, uncompress.c and start.c. To make this more readable and reliable, this patch gathers these information in barebox-arm.h with static inline functions for the calculation of the memory offsets. This patch also adds proper handling of different barebox/board data sizes. Currently only 1MB+Alignment of RAM is reserved for Barebox and board data. This could be too small for bigger devicetrees and barebox. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Fix exception table setup in MMU-less modeAndrey Smirnov2016-01-112-0/+66
| | | | | | | | | | | | | | | | | | | | Add code necessary for correct initialization of exception vector table when MMU is disabled. Note: Only ARMv7 support is implemented Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: Add VBAR setupAndrey Smirnov2016-01-111-0/+10
|/ | | | | | | | | Add code to make sure that normal vector exception table, when it is used due to unavailability of the high vector table, was not re-mapped from 0x0 via VBAR by someone else before us. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/arm'Sascha Hauer2015-12-082-33/+0
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| * ARM: Remove do_execute and thumb2_executeTrent Piepho2015-12-071-26/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 104a6a7ccfb7928ca5dc28c8cbe0ea231ffc45ee support was added for Thumb2. It added do_execute() as a way to provide arch dependent calling veneers for use in "go" and thumb2_execute() as the thumb2 to arm veneer. But thumb2_execute() isn't necessary as gcc generates a proper calling sequence from a standard function pointer call. Thumb2 barebox is compiled with the AAPCS ABI which requires this. It also had a bug and didn't pass the arguments properly, but code execute via "go" rarely uses arguments so this wasn't very noticeable. Since thumb2 was always the only user of do_execute(), go ahead and delete that too. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: don't let the unwinder depend on exception handlingUwe Kleine-König2015-11-091-7/+0
| | | | | | | | | | | | | | | | | | | | To be able to use dump_stack() without support exception handling the definition of dump_stack has to move to a file that is actually compiled without ARM_EXCEPTIONS. Fixes: d332597c7c16 ("ARM: make exception handling optional") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Fix bug in remap_rangeSascha Hauer2015-11-131-16/+22
| | | | | | | | | | | | | | | | | | | | | | remap_range takes generic MAP_CACHED/MAP_UNCACHED flags which are then translated into the corresponding ARM specific bits. We call remap_range internally from dma_alloc_* aswell, but instead of passing the generic flags we pass the ARM specific bits. Fix this by creating an internal __remap_range function which takes the ARM specific bits and use it where appropriate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: calculate compressed dtb len correctlySascha Hauer2015-11-111-1/+1
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/memtest'Sascha Hauer2015-11-061-13/+17
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| * rework remap_rangeSascha Hauer2015-11-031-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | remap_range is for remapping regions with different cache attributes. It is implemented for ARM and PowerPC only, the other architectures only provide stubs. Currently the new cache attributes are passed in an architecture specific way and the attributes have to be retrieved by calls to mmu_get_pte_cached_flags() and mmu_get_pte_uncached_flags(). Make this simpler by providing architecture independent flags which can be directly passed to remap_range() Also provide a MAP_ARCH_DEFAULT flag and a arch_can_remap() function. The MAP_ARCH_DEFAULT defaults to whatever caching type the architecture has as default. the arch_can_remap() function returns true if the architecture can change the cache attributes, false otherwise. This allows the memtest code to better find out what it has to do. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2015-11-061-2/+46
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| * | ARM: Allow compressed dtb binariesSascha Hauer2015-10-271-0/+46
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current multi image build process the DTBs end up uncompressed in the PBL. This can be annoying because the PBL is often very size constrained. This patch allows to put the DTBs in as lzo compressed binary into the PBL. Since lzo offers quite good compression ratios for DTBs no other compression algorithm has been implemented for now. Boards which want to use the compressed DTBs only have to change the __dtb_ prefix in the DTB name to __dtb_z_. Also they should select ARM_USE_COMPRESSED_DTB to make sure barebox supports uncompressing the DTB. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm/cpu: Avoid multiple definitions of barebox_arm_entryAndrey Smirnov2015-11-026-72/+62
| | | | | | | | | | | | | | | | | | | | All versions of barebox_arm_entry (in uncompress.c, start.c and start-pbl.c) appear to be doing exacty the same thing. So move the definition into a separate file and use IS_ENABLED macro to avoid re-definition. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm/cpu/start.c: Distil some common code in __start().Andrey Smirnov2015-11-021-24/+36
| | | | | | | | | | | | | | | | | | | | | | Both barebox_boarddata and barebox_boot_dtb perform essentially the same function -- hold a pointer to a chunk of private data. Since only one variable is ever used at any given time we may as well merge those two variable into one. This also allows us to share more code between two boot paths (board data vs. device tree) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: l2x0: move outer cache flush on disable to userLucas Stach2015-10-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | There are systems like the Calxeda Highbank, which need to do SMC calls in order to access the secure L2C registers, which means they want to replace the outer cache disable function with their own. As the cache flush before entering the boot target is still needed and to avoid exposing L2C internals to the architectures move the flush before disable into the only current user. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: l2x0: correct indentationLucas Stach2015-10-131-2/+2
|/ | | | | | | This is a trivial commit. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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