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* ARM: mmu64: allow to disable null pointer trap on zero pageMichael Tretter2020-10-222-1/+13
| | | | | | | | | | | | | | | | | | Barebox uses the zero page to trap NULL pointer dereferences. However, if the SDRAM starts at address 0x0, this makes the first page of the SDRAM inaccessible and makes it impossible to load images to offset 0x0 in the SDRAM. Trapping NULL pointer dereferences on such systems is still desirable. Therefore, add a function to disable the traps if accessing the zero page is necessary and to re-enable the traps after the access is done. The zero_page_memcpy function simplifies copying to the SDRAM, because this is the most common required functionality, but memtest also accesses the zero page and does not use memcpy. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: Add common device tree register functionSascha Hauer2020-10-121-7/+1
| | | | | | | | The different architectures duplicate some code around unflattening and registering the device tree. Add common functions to reduce this duplication. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: fix NULL pointer dereference on CPU idleAhmad Fatoum2020-10-021-1/+1
| | | | | | | | We guard against cpu_off being NULL, but dereference cpu_suspend instead. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc' into masterSascha Hauer2020-09-252-26/+6
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| * arm/cpu/*.S: Replace license and copyright boilerplate by SPDX identfiersUwe Kleine-König2020-09-152-26/+6
| | | | | | | | | | | | | | | | | | Since commit ed2f892a1ba7 ("arm/cpu: Replace license and copyright boilerplate by SPDX identfiers") my script learned to detect .S files, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Add KASan supportSascha Hauer2020-09-224-6/+11
|/ | | | | | | | | | | | | | This adds KASan support to the ARM architecture. What we are doing is: * Add __no_sanitize_address attribute to various lowlevel functions which do not run in a proper C environment * Add non-instrumented variants of memset/memcpy (prefixed with '__') * make original memcpy/memset weak symbols so strong definitions in lib/kasan/common.c can replace them * Use non-instrumented memcpy in early functions * call kasan_init() Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/module'Sascha Hauer2020-07-271-0/+1
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| * arm: module: Allow modules outside of bl rangeDavid Dgien2020-07-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike the Linux kernel, barebox does not have a dedicated heap for storing modules. Therefore, if the system memory configuration places the general heap further away than can be reached by a 'bl' instruction (24 bits of address, or 16 MiB), then the module relocations will fail due to being out of range. Allocate PLTs when loading modules so that jumps and calls whose targets are too far away for their relative offsets to be encoded in the instructions themselves can be bounced via veneers in the module's PLT. The modules will use slightly more memory, but after rounding up to page size, the actual memory footprint is usually the same. Adoption of Linux commits: 66e94ba3c8ea ARM: kernel: avoid brute force search on PLT generation 1031a7e674d1 ARM: kernel: sort relocation sections before allocating PLTs 05123fef0982 ARM: kernel: allocate PLT entries only for external symbols 35fa91eed817 ARM: kernel: merge core and init PLTs 7d485f647c1f ARM: 8220/1: allow modules outside of bl range Signed-off-by: David Dgien <dgienda125@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm/cpu: Replace license and copyright boilerplate by SPDX identfiersUwe Kleine-König2020-07-1414-186/+39
|/ | | | | | | | | | | | | This adapts all files that were identifed by licensecheck (https://salsa.debian.org/build-common-team/licensecheck.git) as licensed under the GPL. While touching these files also do some minor comment reformatting to get some uniform layout. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kbuild: rename pbl object pbl-*.o to *.pbl.oMasahiro Yamada2020-05-201-6/+6
| | | | | | | | | | | | | | | | | | Currently, pbl objects are output to: <directory-path>/pbl-<basename>.o This commit changes as follows: <directory-path>/<basename>.pbl.o The motivation is not only to get rid of the ugly code introduced by commit 257abdaa36c8 ("Do not rm the path from pbl-y target"), but also to make it easier to remove obj-dtb-y, pbl-dtb-y, lwl-dtb-y syntax in the next commit. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: remove references to CREDITSUwe Kleine-König2020-04-2711-33/+0
| | | | | | | | The CREDITS file was removed from barebox in 2015 by commit 6570288f2d97 ("Remove the CREDITS file"). Remove references to it from several files. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: sm.c: add the attribute 'volatile' to some asm() statements.Giorgio Dal Molin2020-04-141-4/+4
| | | | | | | | Prevent the compiler to eventually cache register values read/written to/from CP15. Signed-off-by: Giorgio Dal Molin <giorgio.nicole@arcor.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: fixed enabling the MMU after switching in non secure mode.Giorgio Dal Molin2020-04-142-1/+12
| | | | | | | | | | | | | | | | | | | | | The Domain Access Control Register (DACR) in CP15 is banked between secure and non secure mode: there a copy of the reg. in secure mode and a second copy in non secure mode. As barebox boots on the imx7 SOC it runs in secure mode and initializes the secure-mode copy of DACR (with 0x00000001). After switching to non secure mode, for example with the command 'smc -n' or while booting a kernel image with global.bootm.secure_state=nonsecure, the active value of DACR is the copy in non-secure mode and that copy was still uninitialized and in an UNKNOWN state. This caused the cpu to hang as soon as the MMU was enabled in non-secure mode. We fix this by reading the DACR value in secure mode just before switching to non secure and then initializing it again with the same value. Signed-off-by: Giorgio Dal Molin <giorgio.nicole@arcor.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Drop unused macros in exceptions.SAndrey Smirnov2020-04-011-28/+0
| | | | | | | | | Those macros looks like a leftover from the time Barebox had some code to deal with IRQs. That code is gone and there are no users for those macros in the codebase anymore. Drop them. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm64: Set PXN/UXN attributes for uncached memSascha Hauer2020-03-313-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The attributes should be set to avoid speculative access to memory-mapped peripherals. The patch has been tested with: noinline unsigned long nox(void) { return get_pc(); } static void xn_test(void) { void *adr = (void *)SOME_SRAM_ADDRESS; unsigned long ret; unsigned long (*fn)(void) = adr; memcpy(adr, nox, 0x1000); sync_caches_for_execution(); ret = fn(); printf("pc: 0x%08lx\n", ret); } Without this patch nox() gets executed in SRAM, with it runs into a abort as expected. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM64: attribute argument to create_sections() is 64bitSascha Hauer2020-03-311-3/+5
| | | | | | | | The attribute argument to create_sections() is 64bit, so pass in a 64bit variable. This is done in preparation for using some of the upper bits in the (UN)CACHED_MEM defines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM64: Setup vectors in all lower execption levelsSascha Hauer2020-03-311-9/+16
| | | | | | | | barebox on ARM64 often changes the exception level when loading a TF-A or other secure monitor firmware. Make sure we have setup the vector table in the exception level we then end up in. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: external NAND boot: Leave icache disabledSascha Hauer2020-02-191-0/+2
| | | | | | | | | | | | | | | It seems running from the NFC SRAM doesn't work with the instruction cache enabled, it leads to corruptions on the i.MX27. We stumbled upon this earlier and the solution at that time was to disable the instruction cache in the NAND boot code. It is, however, more reliable to just not enable the instruction cache in the first place. This is not particularly nice as we have to ifdef this in generic code, duplicate arm_cpu_lowlevel_init(), or call arm_cpu_lowlevel_init() later when we are out of NFC SRAM. From the different bad solutions I chose to ifdef the instruction cache away. It will be enabled later in the common cache functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rpi'Sascha Hauer2020-01-153-2/+39
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| * device: Introduce dma_offsetSascha Hauer2019-12-203-2/+39
| | | | | | | | | | | | | | | | | | | | For devices that do not have a 1:1 mapping between DMA and CPU we need a dma_offset. This adds dma_offset to struct device_d and starts honoring it in ARM dma_(un)map_single(). Also we add some comments to functions that would normally need a device argument to make the DMA <-> CPU translations device specific. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: cache_64: invalidate icache in arm_early_mmu_cache_flushAhmad Fatoum2019-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far arm_early_mmu_cache_flush has only been used in preparation for executing newly-written code. For this reason, on ARMv7 and below, it had always invalidate the icache after the dcache flush. We don't do this on ARM64, but sync_caches_for_execution depends on this, which had this comment that didn't hold true for ARM64: > Despite the name arm_early_mmu_cache_flush not only flushes the > data cache, but also invalidates the instruction cache. It might be worthwhile to decouple dcache flushing from icache invalidation, but for now, align what we do on ARM64 with what we do for 32-bit ARMs. This fixes a potential read of stale instructions when loading second-stage barebox from the PBL with MMU disabled. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: cache_64: invalidate dcache in arm_early_mmu_cache_invalidateAhmad Fatoum2019-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some ARM cores, cache contents are indeterminate after a Power-On Reset. Turning on the MMU on such cores risks interpreting random cache lines as valid, causing hard-to-debug errors. For this reason, we always invalidate the dcache on <= ARMv7. Let's do likewise for ARM64. Newer ARM cores tend to come up with their dcaches invalidated already, but for some, like the Cortex-A72, L2 caches are invalidated dependent on a signal sampled at reset, so better play it safe. The icache invalidate here seems to serve no useful purpose. It's kept for now for symmetry with ARM32. Note that this is wrong should barebox be entered with the MMU enabled, but this is so far not the case with any ARM64 platform we support. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM64: entry: save/restore potentially clobbered registersLucas Stach2019-12-201-5/+7
|/ | | | | | | | | | | While the comment is correct that currently arm_early_mmu_cache_invalidate() is only a call to to v8_invalidate_icache_all() , which doesn't clobber x0-x2, this starts to fall apart as soon as we do something more in this function. Make sure to properly save/restore the parameters passed to the entry function. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/randfixes'Sascha Hauer2019-12-104-15/+5
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| * ARM: psci: declare locally used functions as staticLucas Stach2019-12-021-1/+1
| | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: implement CONFIG_PBL_BREAK for ARM64Lucas Stach2019-12-021-0/+4
| | | | | | | | | | | | | | ARM64 uses a different assembler mnemonic for the breakpoint. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: move into ARM32 specific optee kernel start into lib32 dirLucas Stach2019-12-022-15/+0
| | | | | | | | | | | | | | | | Otherwise it may also get built on a ARM64 config, which obviously fails. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM64: Switch to 4 level page tablesSascha Hauer2019-11-273-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 3 level page tables only allow to resolve 39 bit addresses. Switch to 4 level page tables to add support for bigger physical address ranges. This is needed for example on Layerscape SoCs where the PCI windows are outside the 39bit range. The early MMU support still uses 39bit addressing. We only use a single level page table in early MMU support and with 48bit addresses we wouldn't have enough granularity to map the SDRAM differently then the rest of the address space. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: cpu: dtb: remove unused declarationAhmad Fatoum2019-11-251-2/+0
| | | | | | | | | | | | | | | | | | We no longer use __dtb_start on ARM and the declaration is unused in the file. Drop it. No functional change. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | commands: smc: verify PSCI_POWER_ON with interprocessor handshakeAhmad Fatoum2019-11-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The use of psci_printf here, at least for the phytec-phycore-imx7, is racy, because access to the UART is not synchronized. This may lead to characters being swallowed and most certainly to garbled text. One way around this would be using separate UART ports for each core or even more generically, just dropping psci_printf and resorting to inter-core communication over shared-memory to check whether code execution succeeded. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: psci: factor out smc command into commands/Ahmad Fatoum2019-11-191-105/+0
| | | | | | | | | | | | | | | | | | | | | | So far, the smc command was only usable when barebox also provides the secure monitor. It's useful to have it when barebox is a PSCI consumer as well to test whether the secure monitor works. Factor out the code into commands/ in preparation to do so. No functional change. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: check for machine type lastLucas Stach2019-11-121-11/+11
|/ | | | | | | | | | | A valid DTB may reside low in the Barebox binary address map. If this binary is started at a very low address, we might mistake the pointer for a machine type. Make sure to check for all other possibilities first before interpreting the boarddata as a raw machine type. Fixes: 19c24e2f0121 (ARM: start: Allow to pass machine type as boarddata) Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mmu-early: On i.MX6 with HAB map ROM is mapped without XNSascha Hauer2019-11-081-0/+7
| | | | | | | | | On i.MX6 with HAB enabled we call into the ROM later in imx6_hab_get_status(). This only works when the XN bit is not set for this area, so remap the first MiB as cached which doesn't have the XN bit set. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: implement PSCI client driverAhmad Fatoum2019-11-072-0/+191
| | | | | | | | | | | | System reset on the STM32MP may be done via PSCI when running TF-A as first-stage boot loader. Provide a PSCI driver to simplify using it: - A psci_invoke function is exported, so other code can use it - A fixup for the PSCI device tree node is registered - A reset and poweroff handler via PSCI is registered for PSCI >= v0.2 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: wire in smc command helpAhmad Fatoum2019-11-071-2/+4
| | | | | | | | | | | | | The smc command has a help defined, but unused. Wire it in, so help smc and smc -invalidoption work as expected. While at it, remove the unimplemented -z option. It's unneeded, because -c turns off the CPU after starting it again already. Also it seems it's not implementable without interprocessor communication, which is probably overkill here. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: use CONFIG_ARM_PSCI_DEBUG for smc commandAhmad Fatoum2019-11-071-1/+1
| | | | | | | | | There's already an option to use when debugging PSCI. Instead of requiring users to #define DEBUG 1 as well, have the smc command be usable when CONFIG_ARM_PSCI_DEBUG, not DEBUG is defined. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: translate PSCI error codes in smc commandAhmad Fatoum2019-11-071-1/+37
| | | | | | | | | | For more usability, translate CPU_ON error codes into the error descriptions found in the PSCI Platform Design Document[1]. [1]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mxs'Sascha Hauer2019-10-171-1/+13
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| * ARM: start: Allow to pass machine type as boarddataSascha Hauer2019-10-021-1/+13
| | | | | | | | | | | | | | | | Allow to pass a machine type number as directly as boarddata. This makes it easy for non device tree boards to pass a machine type and to identify themselves during runtime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: use client domain permissions to support ARMv7 eXecute NeverAhmad Fatoum2019-10-143-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual notes[1]: > When using the Short-descriptor translation table format, the XN > attribute is not checked for domains marked as Manager. > Therefore, the system must not include read-sensitive memory in > domains marked as Manager, because the XN bit does not prevent > speculative fetches from a Manager domain. To avoid speculative access to read-sensitive memory-mapped peripherals on ARMv7, let's use client domain permissions for all memory, so the XN bit (and also R/W bits) can function. This aligns us with what Linux is doing on ARMv7. This fixes cache corruption instances that had been observed on the i.MX6UL(L) when the instruction prefetcher speculates into memory following the end of a 512M SDRAM[2]. While this is not necessary to avoid speculative accesses on < ARMv7, we could probably have everything there in client domain as well, but due to lack of test coverage, we'll restrict the change to ARMv7. [1]: B3.7.2 - Execute-never restrictions on instruction fetching [2]: "Cache Corruption on MX6UL(L)": https://community.nxp.com/thread/511925 Fixes: 0198567c4 ("ARM: mmu: mark uncached regions as eXecute never on v7") Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: set R/W bits in ARMv7 translation tableAhmad Fatoum2019-10-141-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | With barebox using the manager permissions for domain 0 that's used for all page table entries and directories, we never had the need so far to explicitly set R/W bits. We did so anyway for sections in the early MMU code, but later on in the normal MMU setup, we didn't do so consistently. In preparation for switching to DOMAIN_CLIENT for ARMv7, configure R/W everywhere in normal MMU code as well. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: cache-armv7: remove duplicate domain initializationAhmad Fatoum2019-10-141-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | We already call set_domain each time we do __mmu_cache_on. Writing the DACR in the armv7 __mmu_cache_on is thus superfluous. Drop it. This changes existing behavior, whereas all 16 memory domains had the same access permissions set (manager) before, now only the first domain has. This is ok, as we only ever use domain 0 in barebox and on non-armv7, we don't bother with the other ones at all. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: cache-armv7: remove superfluous instructionAhmad Fatoum2019-10-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | There are two tst r11, #0xf with nothing in between them that changes r11. This a left over from the kernel code that checks for VMSA twice, once to check if the page table should be setup and once to more to flush the TLB. We do the setup in the caller already, so the tst serves no useful purpose. Delete one. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: remove no longer accurate commentAhmad Fatoum2019-10-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | This comment refers to the state of things prior to e3e54c644 ("ARM: mmu: Implement on-demand PTE allocation"). Since then, we no longer generate 2nd level page tables directly below. Remove it to avoid confusion. Cc: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: use system.h's get_cr() for cpuinfoAhmad Fatoum2019-10-141-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of open-coding the get_cr(), use the already available helper in <asm/system.h> same as we do for 64-bit ARMv8. The only difference is that the "memory" clobber is replaced by "cc". This is ok as we don't expect get_cr() to affect memory and because we do it elsewhere in barebox without a "memory" clobber already. While at it, move it out the #if/#else clause as the helper changes behavior depending on the same CONFIG option anyway. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: aarch64: Re-implement most of barebox_arm_entry() in assemblyAndrey Smirnov2019-10-014-10/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC9 now produces the following warning: common.h:51:2: warning: listing the stack pointer register ‘sp’ in a clobber list is deprecated [-Wdeprecated] 51 | __asm__ __volatile__("mov sp, %0" | ^~~~~~~ common.h:51:2: note: the value of the stack pointer after an ‘asm’ statement must be the same as it was before the statement Stack pointer was added to clobber list in commit f9fc8254b2 ("ARM: Mark SP as being clobbered in arm_setup_stack()") to prevent GCC from generating code that would corrupt 'boarddata' pointer by trying to restore it from invalid stack frame. Interestingly enough, seemingly unrelated change in commit 64d95896cf ("ARM: aarch64: compile with general-regs-only") changed generated code such that adding SP to clobber list became no longer necessary. While the above can probably be a fix by itself, it seems a better and more future proof approach would be to address the problem at its root and re-implement offending startup sequence in assembly. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Merge single pbl with multi pblSascha Hauer2019-10-015-111/+21
| | | | | | | | | | | | | | | | | | So far we have two different implementations for PBL: One for a single PBL and one for multiple images. This patch implements the single PBL case as a special case of the multi PBL case. With this the single PBL becomes a multi PBL image with the entry point start_pbl. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: drop bultin DTBSascha Hauer2019-10-011-6/+0
| | | | | | | | | | | | | | | | We can build multiple DTBs into the binary and board code can select which one to use. Drop the single builtin DTB and let the boards using it pass the correct one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: remove PBL_FORCE_PIGGYDATA_COPYSascha Hauer2019-09-231-13/+0
|/ | | | | | | This option is unused in the tree, remove it for now. If you need this option, let me know, we'll find another solution. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/qemu'Sascha Hauer2019-09-123-0/+148
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