summaryrefslogtreecommitdiffstats
path: root/arch/arm/include
Commit message (Collapse)AuthorAgeFilesLines
* ARM: psci: implement PSCI client driverAhmad Fatoum2019-11-071-2/+21
| | | | | | | | | | | | System reset on the STM32MP may be done via PSCI when running TF-A as first-stage boot loader. Provide a PSCI driver to simplify using it: - A psci_invoke function is exported, so other code can use it - A fixup for the PSCI device tree node is registered - A reset and poweroff handler via PSCI is registered for PSCI >= v0.2 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: Re-implement most of barebox_arm_entry() in assemblyAndrey Smirnov2019-10-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | GCC9 now produces the following warning: common.h:51:2: warning: listing the stack pointer register ‘sp’ in a clobber list is deprecated [-Wdeprecated] 51 | __asm__ __volatile__("mov sp, %0" | ^~~~~~~ common.h:51:2: note: the value of the stack pointer after an ‘asm’ statement must be the same as it was before the statement Stack pointer was added to clobber list in commit f9fc8254b2 ("ARM: Mark SP as being clobbered in arm_setup_stack()") to prevent GCC from generating code that would corrupt 'boarddata' pointer by trying to restore it from invalid stack frame. Interestingly enough, seemingly unrelated change in commit 64d95896cf ("ARM: aarch64: compile with general-regs-only") changed generated code such that adding SP to clobber list became no longer necessary. While the above can probably be a fix by itself, it seems a better and more future proof approach would be to address the problem at its root and re-implement offending startup sequence in assembly. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Kconfig: retire empty <asm/barebox.h>Ahmad Fatoum2019-08-301-4/+0
| | | | | | | With the latest changes, this file is empty on all archs. Drop it. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Kconfig: create Kconfig symbol for ARCH_HAS_DATA_ABORT_MASKAhmad Fatoum2019-08-301-4/+0
| | | | | | | | Other arch-specific features are exposed in Kconfig too, so do here likewise. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Kconfig: create Kconfig symbol for ARCH_HAS_STACK_DUMPAhmad Fatoum2019-08-301-8/+0
| | | | | | | | Other arch-specific features are exposed in Kconfig too, so do here likewise. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: access __boot_cpu_mode with a functionSascha Hauer2019-08-071-1/+2
| | | | | | | | | | | | | | | | __boot_cpu_mode is accessed from barebox_multi_pbl_start() and barebox_single_pbl_start(). These functions may be called at an address different from the address they are linked at. Calculating the address of global variables can yield wrong results when it is done before setup_c() is called. We can't make sure when the address is calculated, OSELAS.Toolchain-2018.12.0 indeed calculates the address after setup_c() is called, but Debian arm-linux-gnueabihf-gcc 8.3.0 does it before setup_c() is called and thus doesn't work. This is solved by accessing __boot_cpu_mode with a wrapper function which we call explicitly after setup_c() is done. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Fix global_variable_offset() for aarch64Sascha Hauer2019-07-161-6/+14
| | | | | | | | | | | | | Not all toolchains use pc relative addresses for global variables. Apparently the gcc 8.3.0 YOCTO toolchain uses absolute addresses. This means can't simply return 0 for global_variable_offset() but instead have to calculate the offset between the compile addresses for global variables and their runtime address. We do this by getting the address of a global variable pc relative explicitely in assembly and substracting that address from the location the C compiler thinks they are. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32'Sascha Hauer2019-07-121-0/+29
|\
| * ARM: sm: move get_gicd_base_address to header for reuseAhmad Fatoum2019-07-041-0/+29
| | | | | | | | | | | | | | | | | | Incoming PSCI implementation for the STM32MP1 needs to get_gicd_base_address as well, so move it to gic.h to avoid code duplication. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | add CONFIG_PBL_BREAK optionOleksij Rempel2019-06-272-0/+8
|/ | | | | | | | With this option barebox will be build with breakpoint instruction in early pbl stage. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/arm'Sascha Hauer2019-06-115-105/+8
|\
| * ARM: Initial OP-TEE supportSascha Hauer2019-06-072-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for OP-TEE, see https://www.op-tee.org/ barebox starts in secure mode as usual. When booting a kernel the bootm code also loads the optee_os binary. Instead of jumping into the kernel barebox jumps into the optee_os binary and puts the kernel execution address into the lr register. OP-TEE then jumps into the kernel in nonsecure mode. The optee_os binary is passed with the -t option to bootm or with global.bootm.tee. Optionally OP-TEE can be compiled into barebox using the builtin firmware feature. Enable the Kconfig option and place or link your tee binary as optee.bin into the firmware directory. The amount of SDRAM which is kept free for OP-TEE is configurable. This patch was tested on a i.MX6 Nitrogen6x board. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: psci: factor out of_psci_fixup() to separate fileSascha Hauer2019-05-131-0/+2
| | | | | | | | | | | | | | | | | | of_psci_fixup() can be used by code which doesn't use the barebox psci implementation, but provides its own PSCI compatible firmware. Factor it out to a separate file to compile it independently of the barebox PSCI implementation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: unify asm/arm-smccc.h and linux/arm-smccc.hSascha Hauer2019-05-131-104/+0
| | | | | | | | | | | | | | | | | | | | Since 2c20674f0c ("ARM: Add code to support SMCCC on AArch64") we have both arch/arm/include/asm/arm-smccc.h and include/linux/arm-smccc.h. The latter was introduced with Kernel commit 680a0873e ("arm: kernel: Add SMC structure parameter") included, so we have to add the parameter for ARM32 aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: introduce sync_caches_for_executionSascha Hauer2019-05-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have several places in the code which which prepares just modified code for execution. This is done differently in all the places, so add a common function to be used by all. Most places called arm_early_mmu_cache_flush(). This function includes invalidating the instruction cache, so doing it again is unnecessary. Sometimes we had arm_early_mmu_cache_flush() inside #ifdef CONFIG_MMU. The ifdef seems unnecessary since we do not have it consistently, so remove the ifdef. Some early i.MX xload code had icache_invalidate() but forgot to flush the caches. Replace the instruction cache invalidation with sync_caches_for_execution(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: include: dma: Zero out DMA coherent memory in no-MMU caseAndrey Smirnov2019-05-211-0/+2
|/ | | | | | | | Add code to match the behavior of dma_alloc_coherent() when CONFIG_MMU is selected. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/arm'Sascha Hauer2019-05-101-0/+20
|\
| * ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init()Andrey Smirnov2019-04-261-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3, SCTLR will be in a state we expect it to be. Add code to reset it to a known state, so we'd always start form clean slate. This is also matches what we've been doing non 64-bit ARMs. Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon appear to have different mask ROM behaviour where it now leaves MMU enabled if no valid boot source is found. Page table it sets up doesn't include DDR range, so trying to bootstrap the device via JTAG/OpenOCD results in an abort. The value for SCTLR_ELx_FLAGS was taken from Linux kernel. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: aarch64: do not use 32bit optimized find bit functionsMichael Tretter2019-05-061-0/+8
|/ | | | | | | | | | | | | | | | The optimized find bit functions are only implemented for 32 bit and are not built on aarch64 systems. Therefore, for example bootchooser cannot be build for aarch64. Select the generic find_bit implementations on aarch64. As the decision, if lib64 or lib32 is build or not, directly depends on CPU_V8, the generic implementation also should be used if CPU_V8 is selected. Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/warnings'Sascha Hauer2019-04-091-0/+1
|\
| * ARM: boards: Harmonize barebox_arm_reset_vector() prototypeSascha Hauer2019-03-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | barebox_arm_reset_vector() is a global function but we never provided a prototype anywhere. The prototypes differ for the different boards, so to provide a common prototype we must harmonize them. void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) Should be suitable for all boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX7: Make sure CNTFRQ is initialized early enoughAndrey Smirnov2019-03-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to make sure that CNTFRQ is initialized before corresponding clocksource driver tries to use it, otherwise we'll end up crashing due to division by zero. We can't convert imx7_timer_init() to be an initcall since it is an i.MX7 specific task, but CPU type information won't be availible until after imx_init() gets executed at postcore_initcall() level. To solve this move all of the necessary code to be a part of imx7_cpu_lowlevel_init(). Note, that original code both hardcoded frequency value to 8MHz as well as tried to write it to the first element of the frequency mode table which appears to be read-only on i.MX7. So while we are at it, simplify the code by adding set_cntfrq() implementation for ARMv7 and copy the code we already using for i.MX8MQ. Fixes: dece70752 ("clocksource: Enable architected timer support for CPU_V7") Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clocksource: Enable architected timer support for CPU_V7Sascha Hauer2019-03-111-0/+19
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* debug_ll: Move pl011 header file to architecture independent placeSascha Hauer2019-03-061-25/+0
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: start: save end of memory passed to start.Tomaz Solc2019-03-041-0/+1
| | | | | | | | Knowing the address of the end of the memory area used by Barebox is useful if PBL stores some extra data after it, so that board init code can later retrieve it from there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2019-02-131-2/+0
|\
| * move umode_t typedef from asm/types.h to linux/types.hAntony Pavlov2019-01-181-2/+0
| | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mmu: Drop custom virt_to_phys/phys_to_virtAndrey Smirnov2019-01-211-5/+0
|/ | | | | | | | | | Neither ARM nor ARM64 define any address mapping functions that differ from default provided for no-MMU configuration. Drop all the extra code and just rely on functions provided in asm/io.h Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: add ENTRY_PROC macro for arm64Michael Tretter2018-12-101-0/+35
| | | | | | | | | | | | | | arm64 has no __naked__ attribute and the compiler adds a function prologue for saving x29 and x30 to the stack for all C functions. This includes functions defined using the ENTRY_FUNCTION macro. Therefore, the stack needs to be setup before entering a C function, which is not possible if the entry is a C function. Provide a macro to implement the entry in assembly to be able to setup the stack before entering the low level entry function. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/missing-prototypes'Sascha Hauer2018-12-073-0/+5
|\
| * ARM: add prototype for mmu_early_disableLucas Stach2018-12-031-0/+1
| | | | | | | | | | | | | | | | | | This is only provided by aarch64 for now and not actually used, but raher than deleting this potentially useful chunk of code, just provide the prototype to shut up the warning. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: ptrace: add mssing show_regs prototype in aarch64 pathLucas Stach2018-12-031-0/+2
| | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add missing prototype for arm_mem_ramoops_get()Sascha Hauer2018-11-121-0/+2
| | | | | | | | | | | | To avoid missing prototype warning. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: images: use piggydataSascha Hauer2018-12-031-1/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | The way we assemble the multi images on ARM is rather complicated and error prone. We currently cat the compressed barebox image behind the PBL executable and need some magic to obtain the size of the payload and also have to do tricks to reliably get a pointer to the compressed image. This patch switches over to compile the compressed payload into the PBL image itself which has proven to work for the single PBL case and for the ARM Linux Kernel aswell. The goal is to unify the single PBL and the multi PBL cases together in the future to get an easier startup path for ARM. This patch has been tested on the i.MX53 QSB, i.MX53 Vincell, Beaglebone black (both MLO and 2nd stage) and a Phytec phyFLEX i.MX6 board. SoCFPGA Arria10 has also be changed slightly with this patch. We used to generate a single image (barebox-socfpga-achilles.img) which was used as xload image and full image. We now instead generate two images: barebox-socfpga-achilles-xload.img and barebox-socfpga-achilles.img, the former loaded by the ROM and the latter loaded by the xload image. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rpi3'Sascha Hauer2018-11-094-0/+299
|\
| * ARM: add file for HYP mode related setupLucas Stach2018-11-051-0/+3
| | | | | | | | | | | | | | | | | | This adds routines to add hyp mode vectors and switch back to HYP mode from SVC. This is needed in both the PBL and Barebox proper. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Roland Hieber <r.hieber@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: safely switch from HYP to SVC mode if requiredLucas Stach2018-11-021-0/+26
| | | | | | | | | | | | | | | | | | This is a port of the Linux safe_svcmode_maskall macro to the Barebox lowlevel init. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Roland Hieber <r.hieber@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: import opcode helpers from Linux kernelLucas Stach2018-11-022-0/+270
| | | | | | | | | | | | | | | | | | Those are needed to generate some of the ARM SEC and VIRT opcodes in a portable way. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Roland Hieber <r.hieber@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/net-switch-mv88e6xxx'Sascha Hauer2018-11-091-1/+1
|\ \
| * | ARM: Do not expose ARMv8 functions on ARMv7Andrey Smirnov2018-10-181-1/+1
| |/ | | | | | | | | | | | | | | | | Assembly implementing current_el(), read_mpidr(), set_cntfrq(), get_cntfrq() and get_cntpct() is ARMv8 specific, so change #if guard protecting it to reflect that fact. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / ARM: Fix missing prototype warningSascha Hauer2018-10-181-0/+2
|/ | | | | | | | | | Fixes Warnings in usage of ENTRY_FUNCTION whith -Wmissing-prototypes enabled: arch/arm/boards/phytec-som-imx6/lowlevel.c:118:14: warning: no previous prototype for 'start_phytec_phycore_imx6ul_som_512mb' [-Wmissing-prototypes] Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Multi PBL: Fix image calculation for certain toolchainsSascha Hauer2018-09-171-0/+2
| | | | | | | | | | | | | The current way to calculate the compressed image position works with the OSELAS toolchains, but not with the Debian/Ubuntu toolchains. For these toolchains &image_end_marker already returns the correct address, adding global_variable_offset() to it is wrong. The solution seems to be to put the image_end_marker into a different object file so that the compiler cannot play any tricks to resolve the address internally in the object file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2018-08-132-0/+10
|\
| * mx5: Implement Spectre v2 workaround for Cortex-A8Fabio Estevam2018-08-101-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 4.18-rc1 kernel the following warning is seen on i.MX51 and i.MX53: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable Implement the suggested workaround by setting the IBE bit in the auxiliary control register, which allows the kernel to flush the BTB properly. Based on commit 7b37a9c732bf ("ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715") from U-Boot. With this patch applied the kernel now reports: CPU0: Spectre v2: using BPIALL workaround Tested on a imx51 babbage. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add code to support SMCCC on AArch64Andrey Smirnov2018-08-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Port SMCCC code from Linux kernel. To accomodate that: - Introduce CONFIG_ARM_SMCCC, to allow enabling the code independent of CONFIG_ARM_SECURE_MONITOR - Bring <linux/arm-smccc.h> in - Add necessary constants to arch/arm/asm-offsets.c Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Mark SP as being clobbered in arm_setup_stack()Andrey Smirnov2018-08-081-1/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not sure why it was working before, but with recent update of AArch64 GCC to 8.1.1 on my Fedora 28 machine, compiling barebox_arm_entry() yields the following assembly: 0000000000002aac <barebox_arm_entry>: 2aac: a9bd7bfd stp x29, x30, [sp, #-48]! 2ab0: d1404023 sub x3, x1, #0x10, lsl #12 2ab4: d1004063 sub x3, x3, #0x10 2ab8: 910003fd mov x29, sp 2abc: 8b000063 add x3, x3, x0 2ac0: a90153f3 stp x19, x20, [sp, #16] 2ac4: aa0003f3 mov x19, x0 2ac8: aa0103f4 mov x20, x1 2acc: f90017e2 str x2, [sp, #40] <-- storing 'boarddata' on old stack 2ad0: 9100007f mov sp, x3 <-- setting up new stack 2ad4: 97ffffdd bl 2a48 <arm_early_mmu_cache_invalidate> 2ad8: f94017e2 ldr x2, [sp, #40] <--- sadness 2adc: aa1403e1 mov x1, x20 2ae0: aa1303e0 mov x0, x19 2ae4: 940000a1 bl 2d68 <barebox_multi_pbl_start> Which result in AArch64 image (i.MX8MQ) not being bootable. With SP marked as clobbered, the above assembly changes to the following: 0000000000002aac <barebox_arm_entry>: 2aac: a9bd7bfd stp x29, x30, [sp, #-48]! 2ab0: d1404023 sub x3, x1, #0x10, lsl #12 2ab4: d1004063 sub x3, x3, #0x10 2ab8: 910003fd mov x29, sp 2abc: a90153f3 stp x19, x20, [sp, #16] 2ac0: 8b000063 add x3, x3, x0 2ac4: aa0003f3 mov x19, x0 2ac8: aa0103f4 mov x20, x1 2acc: f90017a2 str x2, [x29, #40] 2ad0: 9100007f mov sp, x3 2ad4: 97ffffdd bl 2a48 <arm_early_mmu_cache_invalidate> 2ad8: f94017a2 ldr x2, [x29, #40] 2adc: aa1403e1 mov x1, x20 2ae0: aa1303e0 mov x0, x19 2ae4: 940000a1 bl 2d68 <barebox_multi_pbl_start> now x29 is used to access stored x2 which avoids the problem and allows the system to boot correctly. The change is a no-op on AArch32. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2018-06-113-0/+59
|\
| * clocksource: armv8-timer: Convert explicit assembly into helpersAndrey Smirnov2018-06-111-0/+24
| | | | | | | | | | | | | | | | | | | | Move inline assembly related to querying and counter value as well as getting and setting counter frequency register into asm/system.h as well as converting it inot helper functions. This is done to make the code availible to other parts of the system. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add constants and helpers for system counter interfaceAndrey Smirnov2018-06-111-0/+24
| | | | | | | | | | | | | | | | | | Add constants and helpers for system counter interface as can be found in section "I1.3 Generic Timer registers" of "ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture" Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: include: dma: Add missing no-MMU stubsAndrey Smirnov2018-06-111-0/+11
| | | | | | | | | | | | | | | | Add stubs for dma_map_single() and dma_unmap_single() that were needed for no-MMU build for ARM64 to succeed. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-23 11:57:56 +0000