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* lds: Add and use RO_DATA_SECTION macroSascha Hauer2019-10-141-10/+4
| | | | | | | | | We have many different pointer arrays which we put into linker sections and each time there's one added we have to adjust all linker scripts. This adds a common RO_DATA_SECTION define and uses it for all architectures. This makes it easier to add a new linker array. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* lds: create and use BAREBOX_PCI_FIXUP macroSascha Hauer2019-10-141-14/+1
| | | | | | | No need to repeat the pci fixup sections in each linker script. Add a define for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* lds: Move start/end address variables into definesSascha Hauer2019-10-141-19/+2
| | | | | | | | | | | For the older section defines we specify the start and end addresses outside the macro which means we have to repeat them in each linker script. Make the start/end addresses part of the define to simplify things. While at it, add a BAREBOX_ prefix to the INITCALLS and EXITCALLS macros for consistency to the other defines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Sam Ravnborg <sam@ravnborg.org>
* barebox.lds: Remove unnecessary bracesSascha Hauer2019-10-141-2/+2
| | | | | | | The BAREBOX_CLK_TABLE and BAREBOX_DTB macros are defines that do not take a parameter, so we can remove the braces. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Initial OP-TEE supportSascha Hauer2019-06-074-5/+89
| | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for OP-TEE, see https://www.op-tee.org/ barebox starts in secure mode as usual. When booting a kernel the bootm code also loads the optee_os binary. Instead of jumping into the kernel barebox jumps into the optee_os binary and puts the kernel execution address into the lr register. OP-TEE then jumps into the kernel in nonsecure mode. The optee_os binary is passed with the -t option to bootm or with global.bootm.tee. Optionally OP-TEE can be compiled into barebox using the builtin firmware feature. Enable the Kconfig option and place or link your tee binary as optee.bin into the firmware directory. The amount of SDRAM which is kept free for OP-TEE is configurable. This patch was tested on a i.MX6 Nitrogen6x board. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: Add missing includesSascha Hauer2019-03-181-0/+1
| | | | | | | | | Many files in the tree implement functions, but do not include the header files which provide the prototypes for these functions. This means conflicting prototypes remain undetected. Add the missing includes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: semihosting: Fix function prototypeSascha Hauer2019-03-181-1/+1
| | | | | | lsee takes a loff_t pos argument and not a off_t argument. Fix. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stack unwind: Print messages with pr_warningSascha Hauer2018-11-141-2/+2
| | | | | | | print stack traces with pr_err() rather than printf() to make sure they appear in the logs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: unwind: Make locally used function staticSascha Hauer2018-10-231-1/+2
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: unwind: Provide prototypes for exported functionsSascha Hauer2018-10-231-0/+4
| | | | | | | | __aeabi_unwind_cpp_prx are provided to make the linker happy. To fix warnings about missing prototypes just provide a prototype in the same file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: legacy Linux support: Make locally used functions staticSascha Hauer2018-10-231-3/+3
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2018-08-131-0/+7
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| * bootm: allow booting SoCFPGA prebootloader imageEnrico Jorns2018-08-081-0/+7
| | | | | | | | | | | | | | | | | | A prebootloader image might also contain a fully working barebox and allows to be booted second stage. Thus we add a handler here to give it a try. Signed-off-by: Enrico Jorns <ejo@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | pci: add quirk infrastructureLucas Stach2018-08-081-0/+12
|/ | | | | | | | | This is a cut down version of the Linux kernel PCI quirk infrastructure, which allows to register and execute some fixups before the driver is loaded. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/kill-oftree-f'Sascha Hauer2018-07-091-1/+14
|\ | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: bootm: Add option boot using ATAGsSascha Hauer2018-06-111-5/+21
| | | | | | | | | | | | | | | | | | So far we can only force legacy boot using ATAGs by executing 'oftree -f'. Said command is going away as often this command is not safe to call. Add an alternative way using the global.bootm.boot_atag environment variable. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | bootm: Split bootm_load_devicetree into two functionsSascha Hauer2018-06-151-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | It is not always desired to get the devicetree from image data and load it to a SDRAM region at the same time. Sometimes it's enough to just load it to an allocated address (in case the user has no constraints where the devicetree should be placed. This patch splits bootm_load_devicetree into bootm_get_devicetree which returns a pointer to the allocated devicetree and bootm_load_devicetree which loads the devicetree to a specified region. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: bootm: drop usage of data->oftreeSascha Hauer2018-06-151-19/+24
|/ | | | | | | data->oftree can be replaced with a variable local to the arm code, so drop usage of data->oftree. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: disable 32bit boot commandsSascha Hauer2018-04-043-0/+666
| | | | | | | | The 32bit boot support is full of legacy cruft. While it should be possible to merge the aarch64 support there, a fresh start looks more promising. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: remove ld_var supportSascha Hauer2018-03-211-32/+0
| | | | | | Now that ld_var is no longer used it can be removed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: move away from ld_varSascha Hauer2018-03-211-13/+10
| | | | | | | | | | | | | | The ld_var solves the issue that when compiled with -pie the linker provided variables are all 0x0. This mechanism however refuses to compile with aarch64 support. This patch replaces the ld_var mechanism with a nice little trick learned from U-Boot: Instead of using linker provided variables directly with "__bss_start = ." we put a zero size array into a separate section and use the address of that array instead of the linker variable. This properly works before relocation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: return positive offset in get_runtime_offset()Sascha Hauer2018-03-211-2/+2
| | | | | | | | | | | When we are linked at 0x0 and running at 0x01000000 then get_runtime_offset() should return 0x01000000 and not 0xff000000. This makes get_runtime_offset() more consistent and better understandable. This was tested on a Freescale i.MX53 Quickstart board. Additionally relocate_to_adr() was tested since that is normally not called. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ratp: implement generic command supportAleksander Morgado2018-03-011-0/+4
| | | | | | | | | | | | | | | | | | | The RATP implementation now allows executing generic commands with a binary interface: binary requests are received and binary responses are returned. Each command can define its own RATP request contents (e.g. to specify command-specific options) as well as its own RATP response contents (if any data is to be returned). Each command is associated with a pair of numeric unique request and response IDs, and for easy reference these IDs are maintained in the common ratp_bb header. Modules may override generic implemented commands or include their own new ones (as long as the numeric IDs introduced are unique). Signed-off-by: Aleksander Morgado <aleksander@aleksander.es> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: align exception vectors to 32 byteLucas Stach2017-03-031-1/+1
| | | | | | | | | | | On ARMv7 the exception vectors inside the barebox binary are used directly by remapping the vectors base through the VBAR register. While VBAR allows to remap the exception vectors freely, it still imposes a minimum alignment of 32 byte, as the lower bits are treated as the exception vector offset. Enforce this alignment inside the barebox binary. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2017-02-133-2/+25
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| * ARM: Add PSCI supportSascha Hauer2017-02-133-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains the barebox implementation for the ARM "Power State Coordination Interface" (PSCI). The interface is aimed at the generalization of code in the following power management scenarios: * Core idle management. * Dynamic addition and removal of cores, and secondary core boot. * big.LITTLE migration. * System shutdown and reset. In practice, all that's currently implemented is a way to enable the secondary core one some SoCs. With PSCI the Kernel is either started in nonsecure or in Hypervisor mode and PSCI is used to apply power to the secondary cores. The start mode is passed in the global.bootm.secure_state variable. This enum can contain "secure" (Kernel is started in secure mode, means no PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available) or "hyp" (Kernel is started in hyp mode, meaning it can support virtualization). We currently only support putting the secure monitor code into SDRAM, which means we always steal some amount of memory from the Kernel. To keep things simple for now we simply keep the whole barebox binary in memory The PSCI support has been tested on i.MX7 only so far. The only supported operations are CPU_ON and CPU_OFF. The PSCI and secure monitor code is based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: Fix image size calculationSascha Hauer2017-02-082-1/+2
|/ | | | | | | | | | In barebox_non_pbl_start() we do not run at the address we are linked at, so we must read linker variables using ld_var(). Since ld_var() current is not available on arm64 we create two zero sized arrays, one at the begin of the image and one at the end. The difference between both is the image size we are looking for. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2016-07-111-4/+8
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* arm: rework lib directory to support arm64Raphael Poggi2016-07-0626-0/+3162
This commit create a common directory, lib/, for arm and arm64 common code. It also create lib32/ and lib64/ for 32bit and 64bit code respectively. Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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