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aarch64 has its own image format. Add a bootm handler to handle this
format. Also add a barebox handler.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Implement stacktraces as a great debugging aid. On aarch64 this is cheap
enough to be enabled unconditionally. Unwinding code is taken from the
Kernel.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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CONFIG_ARM_UNWIND does not exist for aarch64. Remove the dead code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The ld_var solves the issue that when compiled with -pie the linker
provided variables are all 0x0. This mechanism however refuses to
compile with aarch64 support.
This patch replaces the ld_var mechanism with a nice little trick
learned from U-Boot: Instead of using linker provided variables
directly with "__bss_start = ." we put a zero size array into
a separate section and use the address of that array instead of
the linker variable. This properly works before relocation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The RATP implementation now allows executing generic commands with a
binary interface: binary requests are received and binary responses
are returned.
Each command can define its own RATP request contents (e.g. to specify
command-specific options) as well as its own RATP response contents
(if any data is to be returned).
Each command is associated with a pair of numeric unique request and
response IDs, and for easy reference these IDs are maintained in the
common ratp_bb header. Modules may override generic implemented
commands or include their own new ones (as long as the numeric IDs
introduced are unique).
Signed-off-by: Aleksander Morgado <aleksander@aleksander.es>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patch contains the barebox implementation for the ARM
"Power State Coordination Interface" (PSCI).
The interface is aimed at the generalization of code in the following
power management scenarios:
* Core idle management.
* Dynamic addition and removal of cores, and secondary core boot.
* big.LITTLE migration.
* System shutdown and reset.
In practice, all that's currently implemented is a way to enable the
secondary core one some SoCs.
With PSCI the Kernel is either started in nonsecure or in Hypervisor
mode and PSCI is used to apply power to the secondary cores.
The start mode is passed in the global.bootm.secure_state variable. This
enum can contain "secure" (Kernel is started in secure mode, means no
PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available)
or "hyp" (Kernel is started in hyp mode, meaning it can support
virtualization).
We currently only support putting the secure monitor code into SDRAM,
which means we always steal some amount of memory from the Kernel.
To keep things simple for now we simply keep the whole barebox binary in
memory
The PSCI support has been tested on i.MX7 only so far. The only
supported operations are CPU_ON and CPU_OFF.
The PSCI and secure monitor code is based on the corresponding U-Boot
code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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ARM64 has native instructions for division and thus doesn't need the
helper functions implemented in those files.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This commit create a common directory, lib/,
for arm and arm64 common code.
It also create lib32/ and lib64/ for 32bit
and 64bit code respectively.
Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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