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* ARM: Add arm64 pbl udelaySascha Hauer2019-03-132-1/+18
| | | | | | | PBL often needs a way to udelay execution. Since we have a generic timer in ARMv8 we can implement a generic udelay. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2019-02-131-0/+12
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| * ARM: aarch64: Add PCI fixups section to linker scriptAndrey Smirnov2019-02-111-0/+12
| | | | | | | | | | | | | | | | Add PCI fixups section to linker script, so it would be possible to enable PCI support. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: aarch64: Avoid relocations in runtime-offset.SAndrey Smirnov2019-02-011-1/+13
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since get_runtime_offset() is executed as a part of reloaction logic, it cannot have code dependend on any kind of relocation. Unfortunately, current codebase violates this rule and linkadr: .quad get_runtime_offset ends up producing R_AARCH64_RELATIVE relocation that has to be resolved at runtime. From tiral and error experimentation it seems that the simplest way to do this is to drop "a" (allocatable) attribute fom the section directive in runtime-offset.S With "a" (see first entry): aarch64-linux-gnu-objdump -R images/start_zii_imx8mq_dev.pbl images/start_zii_imx8mq_dev.pbl: file format elf64-littleaarch64 DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE 00000000000000b0 R_AARCH64_RELATIVE *ABS*+0x00000000000000a0 0000000000004258 R_AARCH64_RELATIVE *ABS*+0x0000000000028118 0000000000004260 R_AARCH64_RELATIVE *ABS*+0x0000000000028128 00000000000042e0 R_AARCH64_RELATIVE *ABS* 00000000000042e8 R_AARCH64_RELATIVE *ABS*+0x0000000000028118 00000000000042f0 R_AARCH64_RELATIVE *ABS*+0x00000000000042c8 Without "a": aarch64-linux-gnu-objdump -R images/start_zii_imx8mq_dev.pbl images/start_zii_imx8mq_dev.pbl: file format elf64-littleaarch64 DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE 0000000000004258 R_AARCH64_RELATIVE *ABS*+0x0000000000028100 0000000000004260 R_AARCH64_RELATIVE *ABS*+0x0000000000028110 00000000000042e0 R_AARCH64_RELATIVE *ABS* 00000000000042e8 R_AARCH64_RELATIVE *ABS*+0x0000000000028100 00000000000042f0 R_AARCH64_RELATIVE *ABS*+0x00000000000042c8 Note that on recent toolchains (tested on 8.1.1), this problem is masked by the fact that .quad get_runtime_offset will be initialized with link-time value of "get_runtime_offset" in addition to having a R_AARCH64_RELATIVE relocation. 00000000000000a0 <get_runtime_offset>: a0: 10000000 adr x0, a0 <get_runtime_offset> a4: 58000061 ldr x1, b0 <linkadr> a8: eb010000 subs x0, x0, x1 ac: d65f03c0 ret 00000000000000b0 <linkadr>: b0: 000000a0 .word 0x000000a0 b4: 00000000 .word 0x00000000 _However_, older toolchains (tested on 5.5.0), will only issue a R_AARCH64_RELATIVE, so memory location will contain only zeroes: 00000000000000a0 <get_runtime_offset>: a0: 10000000 adr x0, a0 <get_runtime_offset> a4: 58000061 ldr x1, b0 <linkadr> a8: eb010000 subs x0, x0, x1 ac: d65f03c0 ret 00000000000000b0 <linkadr>: ... This leads to an very early crash and complete boot failure in the latter case. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: lib64: .gitignore barebox.ldsMichael Tretter2018-12-101-0/+1
| | | | | | | | | | | | | | Commit e1287b1a8b27 ("arm: rework lib directory to support arm64") restructured the lib directory and added the lib64 directory. It moved the existing .gitignore to the lib32 directory but didn't add a new .gitignore for lib64. Thus building Barebox for arm64 results in stray barebox.lds files. Copy the .gitignore from lib32 to lib64. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM64: backtrace: fix missing prototypesLucas Stach2018-12-031-1/+2
| | | | | | | | Include header for unwind_backtrace prototype and mark dump_backtrace_entry as static. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/bootm'Sascha Hauer2018-07-091-1/+11
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| * bootm: Split bootm_load_devicetree into two functionsSascha Hauer2018-06-151-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | It is not always desired to get the devicetree from image data and load it to a SDRAM region at the same time. Sometimes it's enough to just load it to an allocated address (in case the user has no constraints where the devicetree should be placed. This patch splits bootm_load_devicetree into bootm_get_devicetree which returns a pointer to the allocated devicetree and bootm_load_devicetree which loads the devicetree to a specified region. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: lib64: Make string functions aware of MMU configurationAndrey Smirnov2018-06-114-6/+28
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimized version of memset() in memset.S if called as: memset(foo, 0, size) will try to explicitly zero out data cache with: dc zva, dst which will result in Alignement Exception (DABT) if MMU is not enabled. For more info see: - C4.4.8 "DC ZVA, Data Cache Zero by VA" - D5.2.8 "The effects of disabling a stage of address translation" in "ARM Architecture Reference Manual. ARMv8, for ARMv8-A architecture profile" In similar vein, using optimized version of memcpy() could lead to a unaligned 16-byte write (using 'stp'), which is not allowed for Device-nGnRnE type of memory (see D5.2.8) and would liead to Alignement Exception. To fix both problems expose non-optimized and optimzied versions of the function and created a wrapper to dispatch the call to either one based on if MMU is enabled or not. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: Add support to start kernel and bareboxSascha Hauer2018-04-041-22/+98
| | | | | | | aarch64 has its own image format. Add a bootm handler to handle this format. Also add a barebox handler. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: implement stacktracesSascha Hauer2018-03-292-0/+87
| | | | | | | | Implement stacktraces as a great debugging aid. On aarch64 this is cheap enough to be enabled unconditionally. Unwinding code is taken from the Kernel. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: remove dead code in linker scriptSascha Hauer2018-03-291-16/+0
| | | | | | CONFIG_ARM_UNWIND does not exist for aarch64. Remove the dead code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: Add runtime-offsetSascha Hauer2018-03-212-0/+20
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: move away from ld_varSascha Hauer2018-03-211-13/+9
| | | | | | | | | | | | | | The ld_var solves the issue that when compiled with -pie the linker provided variables are all 0x0. This mechanism however refuses to compile with aarch64 support. This patch replaces the ld_var mechanism with a nice little trick learned from U-Boot: Instead of using linker provided variables directly with "__bss_start = ." we put a zero size array into a separate section and use the address of that array instead of the linker variable. This properly works before relocation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ratp: implement generic command supportAleksander Morgado2018-03-011-0/+4
| | | | | | | | | | | | | | | | | | | The RATP implementation now allows executing generic commands with a binary interface: binary requests are received and binary responses are returned. Each command can define its own RATP request contents (e.g. to specify command-specific options) as well as its own RATP response contents (if any data is to be returned). Each command is associated with a pair of numeric unique request and response IDs, and for easy reference these IDs are maintained in the common ratp_bb header. Modules may override generic implemented commands or include their own new ones (as long as the numeric IDs introduced are unique). Signed-off-by: Aleksander Morgado <aleksander@aleksander.es> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Add PSCI supportSascha Hauer2017-02-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains the barebox implementation for the ARM "Power State Coordination Interface" (PSCI). The interface is aimed at the generalization of code in the following power management scenarios: * Core idle management. * Dynamic addition and removal of cores, and secondary core boot. * big.LITTLE migration. * System shutdown and reset. In practice, all that's currently implemented is a way to enable the secondary core one some SoCs. With PSCI the Kernel is either started in nonsecure or in Hypervisor mode and PSCI is used to apply power to the secondary cores. The start mode is passed in the global.bootm.secure_state variable. This enum can contain "secure" (Kernel is started in secure mode, means no PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available) or "hyp" (Kernel is started in hyp mode, meaning it can support virtualization). We currently only support putting the secure monitor code into SDRAM, which means we always steal some amount of memory from the Kernel. To keep things simple for now we simply keep the whole barebox binary in memory The PSCI support has been tested on i.MX7 only so far. The only supported operations are CPU_ON and CPU_OFF. The PSCI and secure monitor code is based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm64: drop unneeded files from MakefileLucas Stach2016-10-041-2/+0
| | | | | | | | ARM64 has native instructions for division and thus doesn't need the helper functions implemented in those files. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: rework lib directory to support arm64Raphael Poggi2016-07-067-0/+692
This commit create a common directory, lib/, for arm and arm64 common code. It also create lib32/ and lib64/ for 32bit and 64bit code respectively. Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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