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ROM-Code passes boot source information in r4. First stage does likewise
when invoking second stage. When net booting second stage, r4 has no
definite value. Fix this and pass the original boot source along.
This gives us a valid $bootsource value in net booted barebox, which is
important, so the same environment is loaded.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The BootROM passes us information about the boot medium in r4 and we
already use that in first stage and pass it along to second stage
PBL already. To make use of it, we need to pass it to barebox proper, do
this by writing it in the last 4 bytes of the SRAM. As second stage
always run in DRAM, this is safe to do.
We could also write to SRAM directly from first stage, but at91bootstrap
passes info in r4 as well for the sama5d3 boards, so we do it likewise
to maintain compatibility.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Without reconfiguration of the AIC redirection, the OS interrupt
handling will misbehave later on. Add it to the SoC init.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The L2 cache controller needs some initialization before use. Same goes
for the CAN SRAM, do so after the MMU setup.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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