barebox - barebox master repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	pinctrl: i.MX7: Fix LPSR sel_imput setting	Sascha Hauer	2017-02-06	1	-0/+8
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	The i.MX7 has two pinmux controllers, the regular and the LPSR controller. The LPSR pinmux controller doesn't have any sel_input registers, instead they can be found in the regular pinmux controller. This means whenever we want to apply the the sel_input setting for the LPSR controller, we have to apply them to the regular controller instead. In barebox take the easy way out and just add the difference of the two base addresses to the register offset. The same issue is present in the Kernel aswell, but when the bootloader already configured the pins correctly nobody notices when the Kernel sel_input setup effectively is a no-op. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	i.MX: iomuxv3: Add low-level pad configuration routine	Andrey Smirnov	2017-01-12	1	-0/+17
\| \| \| \| \| \| \| \|	Add low-level pad configuration routine that can be used by early boot code as well as leveraged by pinmux driver. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	i.MX: iomuxv3: Add helper macros to deconstruct iomux_v3_cfg_t values	Andrey Smirnov	2017-01-12	1	-0/+8
\| \| \| \| \|	Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	i.MX: iomuxv3: Add low-level pad code to headers	Andrey Smirnov	2017-01-12	1	-0/+28
\| \| \| \| \| \| \| \| \|	Add a basic low-level pad configuration function that can be used to implement early boot pin configuration code as well as shared with various iomuxv3 and vf610 drivers. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: i.MX: Make mxc_iomux_v3_setup_multiple_pads argument const	Sascha Hauer	2014-02-20	1	-1/+1
\| \| \| \|	Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	Treewide: remove address of the Free Software Foundation	Sascha Hauer	2012-09-17	1	-4/+0
\| \| \| \| \| \| \|	The FSF address has changed in the past. Instead of updating it each time the address changes, just drop it completely treewide. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM i.MX iomux-v3: one bit more for pad_ctl	Sascha Hauer	2012-04-12	1	-5/+5
\| \| \| \| \| \|	i.MX6 needs one bit more for PAD_CTRL, so make one free. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM i.MX iomux-v3: Sync to kernel	Sascha Hauer	2012-04-12	1	-31/+47
\| \| \| \| \| \| \| \|	This means using an uint64_t instead of a struct pad_desc which allows us to change pad settings using logic operations. Also with this we can more easily keep the iomux tables in sync with the kernel. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM i.MX: sync i.MX25 iomux support with kernel	Sascha Hauer	2011-03-03	1	-21/+16
\| \| \| \| \| \| \| \|	At least partly. We have pads in barebox that we do not have in the kernel. Also, this with this patch we do not set the sion bit which the kernel does. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM i.MX: Add basic i.MX51 support	Sascha Hauer	2010-10-11	1	-3/+7
\| \| \| \|	Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	i.MX35: Fix pad control bit positions	Juergen Beisert	2010-02-01	1	-15/+15
\| \| \| \| \| \| \| \| \| \| \|	Using these macros simplify the configuration for special GPIO usage. But they should use correct bit positions for usage in the IOMUX_PAD() macro. Note: These are the bit positions of the i.MX35 CPU. Not checked for the other i.MX3x CPUs. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach	Jean-Christophe PLAGNIOL-VILLARD	2009-10-22	1	-0/+107
	Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>