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* ARM: i.MX: esdctl: Add missing compatibleSascha Hauer2020-11-131-0/+3
| | | | | | | The i.MX8mm has "fsl,imx8mm-ddrc" as compatible, add it to the list of matching nodes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mtd-nand'Sascha Hauer2020-11-102-0/+2
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| * mtd: nand: Update to Linux-5.9Sascha Hauer2020-11-102-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This updates the barebox NAND layer and parts of the mtd layer to Linux-5.9. This patch is huge, but the barebox NAND layer is so far away from the Linux NAND layer that a step by step update would have taken ages. Unlike Linux barebox has functions to mark a block as good. This feature has been preserved. Also barebox used to make NAND write support optional, this feature is lost during the update for the sake of better compatibility to the Linux NAND layer. This patch has been tested: - GPMI aka nand_mxs on i.MX6 - nand_imx on i.MX25 - nand_omap_gpmc on AM335x - atmel_nand on Atmel sama5d3 - nand_denali on SoCFPGA Currently untested: - nand_orion - nand_mrvl_nfc - nand_s3c24xx The nand_denali driver is tested with the update of that driver to Linux-5.9 following in the next patch. I could only test the drivers with the NAND chips found on my boards, so there's still enough room for regressions, especially given that the NAND drivers themselves are mostly not updated. With the NAND layer being up-to-date with Linux it should hopefully be easy to update drivers to their Linux counterpart as well if necessary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm: imx: Convert mach headers to SPDXUwe Kleine-König2020-11-0219-272/+51
| | | | | | | | | | | | | | | | Replace license and copyright boilerplate by SPDX identfiers for files identified as GPL-2.0-only or GPL-2.0-or-later by licensecheck. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | imx: Fix copyright claimUwe Kleine-König2020-11-021-12/+2
| | | | | | | | | | | | | | | | | | | | | | The file was created by me in commit c0fcf4dde3c9 ("ARM: i.MX7: provide DDR register definitions") and obviously I failed to adapt our copyright template. While at it, convert to SPDX. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx' into masterSascha Hauer2020-10-143-3/+1073
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| * | ARM: imx: Add Support for Webasto ccbv2Rouven Czerwinski2020-10-143-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Webasto Common Communication Board Version 2. The device tree included with barebox can eventually be replaced with the required barebox changes when the ccbv2 device tree is upstream. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX6UL: add iomux header for i.MX6ULRouven Czerwinski2020-10-091-0/+1064
| | | | | | | | | | | | | | | | | | | | | Add the iomux definitions for the i.MX6UL, taken from U-Boot v2020.10-rc3. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARCH: i.MX6: add support for OFDEVICEMarco Felsch2020-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The imx23_defconfig, imx_v8_defconfig and imx_defconfig already selecting this config except for the imx_v7_defconfig. The imx_v7_defconfig selects MACH_ZII_VF610_DEV which selects ARCH_VF610 which select OFDEVICE. So it will be never selected if the MACH_ZII_VF610_DEV board support is dropped. Selecting the option here seems to be the better place instead of adding it to the imx_v7_defconfig because there are possible no i.MX6 boards not using the device tree. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX6X: cleanup build dependencyMarco Felsch2020-10-051-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Both dependencies are covered by ARCH_IMX6 so we no longer need to mention them here too. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: phytec-som-imx6: fix build dependencyMarco Felsch2020-10-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable i2c support since the board code configures the i2c connected PMIC. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/driver-macro' into masterSascha Hauer2020-10-142-13/+2
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| * | treewide: Use driver macroSascha Hauer2020-09-292-13/+2
| |/ | | | | | | | | | | | | We have several macros for a oneline driver registration. Add some missing and use them consistently where possible througout the tree. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / ARM: cm-fx6: fix build dependencyMarco Felsch2020-10-051-0/+1
|/ | | | | | | | The cm-fx6 board uses the edhc-pbl function during lowlevel init. So we need to select it. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx' into masterSascha Hauer2020-09-254-56/+72
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| * arch: arm: mach-imx: Add habv4 config file for i.MX6ULLMaik Otto2020-09-233-56/+71
| | | | | | | | | | | | | | | | | | The i.MX6ULL has no CAAM engine for Secure Boot on HABv4 (NXP AN4581). For i.MX6ULL the engine Software (SW) must used for the image validation. Signed-off-by: Maik Otto <m.otto@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * arm: imx: Select RELOCATABLE on IMX_MULTI_BOARDSLars Pedersen2020-09-231-0/+1
| | | | | | | | | | | | | | | | Depend on RELOCATABLE when compiling for multiple i.MX boards, since setting a suitable TEXT_BASE value across multiple boards is impossible. Signed-off-by: Lars Pedersen <lapeddk@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: imx8m: Make uart setup function name more genericSascha Hauer2020-08-211-1/+1
|/ | | | | | | | So far all i.MX8M variants have the same UART base addresses, so let's be optimistic that it stays like that and rename imx8mq_uart_setup() to imx8m_uart_setup(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx8m: make debug UART selection available on i.MX8MM/MPLucas Stach2020-08-174-18/+3
| | | | | | | | | i.MX8MM/MN/MP has UARTs in the same place in the MMIO address space as the i.MX8MQ, so make the lowlevel debug a bit more generic across the i.MX8M family. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx8mm: select FIRMWARE_IMX_LPDDR4_PMU_TRAIN from IMX8MM_EVKLucas Stach2020-08-171-0/+1
| | | | | | | | Without this select the necessary DDR PHY firmware files will be missing when only building for the i.MX8MM-EVK board. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: Add atlascopco sxb boardAnees Rehman2020-08-101-0/+6
| | | | | Signed-off-by: Anees Rehman <anees.r3hman@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc-pbl: Add support for IMX7Anees Rehman2020-08-101-0/+1
| | | | | Signed-off-by: Anees Rehman <anees.r3hman@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: boards: add initial imx8mp-evk supportOleksij Rempel2020-07-142-0/+14
| | | | | | | | | | This adds support for the NXP i.MX8MP-EVK board. The SDRAM timings are taken from U-Boot-2020.07-rc4, other information how to initialize the board are form U-Boot as well. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: bbu: Fix IVT offset for i.MX8MPSascha Hauer2020-07-141-6/+11
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc-pbl: Add imx8mp_esdhc_load_image() for i.MX8MPSascha Hauer2020-07-141-0/+1
| | | | | | | | | | | | | | | | | | | The image format of the i.MX8MP is different from i.MX8M, so add its own image loading function for it. Older i.MX SoCs had a IVT Offset (the offset from the start of the image to the actual data) of 1KiB. This was done to leave space for the partition table at the beginning of the device. To support GPT SoCs starting with i.MX8M an additional gap of 32KiB was added, so that the actual image started at offset 33KiB. Now starting with i.MX8MP the now superfluous 1KiB offset was removed do that the actual image now starts at 32KiB. Unfortunately the 1KiB offset is woven into the offsets of the IVT whereas the 32KiB are not, which means that we really have to handle both offsets individually instead of just handling the sum of the offsets. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: imx: add initial imx8mp supportOleksij Rempel2020-07-1415-3/+1247
| | | | | | | | | | | | This adds base support for the i.MX8MP SoC. Not much to do here as this SoC is quite similar to the i.MX8M. This adds: - Kconfig symbols - bootsource detection - register base address defines - iomux defines Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
* scripts: imx-image: rename image_dcd_offset to image_ivt_offsetSascha Hauer2020-07-141-1/+1
| | | | | | | | | image_dcd_offset is a misnomer, it should really be image_ivt_offset. The DCD (Device Configuration Data) is only one part of the data linked into the IVT (Image Vector Table), but the meaning of the variable is really the latter, not the former. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: add imx6 based Protonic boadsOleksij Rempel2020-06-181-0/+6
| | | | | | | Add initial support for 15 i.MX6 based Protonic boards. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Arm: i.MX5: Do not disable L2 cacheSascha Hauer2020-06-181-2/+5
| | | | | | | | | | | | | | Disabling the L2 cache is not working in imx5_init_lowlevel() because the necessary cache maintenance operations are missing. This often results in cache corruption in a chainloaded barebox. Disabling the cache is unnecessary: when we come from the ROM the L2 cache is disabled anyway, so disabling it is a no-op. When we get here in a chainloaded barebox the L2 cache is already enabled and correctly configured. So instead of initializing it again we can take an enabled L2 cache as a sign to skip initialization and just return from the function. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2020-06-111-4/+4
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| * treewide: replace commas with semicolons where appropriateAhmad Fatoum2020-05-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Found by searching drivers/ arch/ common/ and lib/ for /^\s+[^."/\*\[\s\{\(A-Z][^\[\{\(]*=[^\{\(]+,$/ Because the comma has the lowest precedence in C, this shouldn't result in any functional change. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX: enable Master Identifier UnlockRouven Czerwinski2020-06-022-2/+2
|/ | | | | | | | | | | | | | By default the HAB locks the Master Identifier (MID) to preconfigured values. This is not a problem if Linux is running in the secure world, however when running a secure world operating system such as OP-TEE, the MID configuration should be done by the secure world operating system. This causes no regressions for systems using no secure world operating systems, since no MID value indicates that all normal/secure world entities can access the peripherals supporting the MID. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX6: boot: handle i.MX6UL differencesAhmad Fatoum2020-05-121-0/+3
| | | | | | | | | | | | | | | | | | | The i.MX6UL differs from the i.MX6Q in the interpretation of the first two values for BOOT_CFG(7, 4): +--------------+----------+----------+ |BOOT_CFG1(7,4)| 0x01 | 0x02 | |==============+==========+==========| | MX6Q | reserved | SATA | |--------------+----------+----------| | MX6UL | QSPI | reserved | +--------------+----------+----------+ The reserved (forced serial) values are handled in the previous commit. Add QSPI boot source detection now. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: boot: interpret reserved boot as forced serialAhmad Fatoum2020-05-122-4/+19
| | | | | | | | | | | | | | | `mw 0x20d8040 0x00000010; mw 0x20d8044 0x10000000; reset` issued on an i.MX6Q forces serial download mode, but there is no indication of that in the sbmr2 register, so barebox reports $bootsource=unknown. Similarly, `mw 0x20d8040 0x00000020; mw 0x20d8044 0x10000000; reset` forces an i.MX6UL into recovery mode after reset. Do as U-Boot does and interpret the (reserved) value in BOOT_CFG1(7, 4) for each SoC as serial download. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: boot: correctly handle SRC_SBMR1 override via SRC_GPR9Ahmad Fatoum2020-05-081-6/+19
| | | | | | | | | | | | | `mw 0x20d8040 0x08000030; mw 0x20d8044 0x10000000; reset` issued on an i.MX6Q forces boot from the ecspi1. This is because the BootROM reads the boot mode out of SRC_GPR9 instead of SRC_SBMR1 whenever SRC_GPR10 has its 28th bit set. Teach barebox about this, so we don't end up with a wrong $bootsource when putting SRC_GPR9 into use. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: configurable Super Root Key indexRouven Czerwinski2020-05-083-2/+12
| | | | | | | | Allow the configuration of the Super Root Key Index, to let the user select another key if a previous key has been revoked. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: remove references to CREDITSUwe Kleine-König2020-04-278-24/+0
| | | | | | | | The CREDITS file was removed from barebox in 2015 by commit 6570288f2d97 ("Remove the CREDITS file"). Remove references to it from several files. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zii-common: Add common environment directoryAndrey Smirnov2020-04-031-0/+1
| | | | | | | | | | Establish a common environment directory between all ZII boards, so that we could share common bits and pieces. As a first step, get rid of board scecific net boot scripts and replace them with a single shared one. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32'Sascha Hauer2020-03-181-1/+1
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| * reset_source: migrate from reset_source_name to reset_source_to_stringAhmad Fatoum2020-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | Whether reset_source_name() returns the just set reset_source is dependent on probe order and the priorities of prior reset sources in relation to the current one. Make this more robust by using the new reset_source_to_string. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2020-03-1829-349/+1353
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| * | ARM: i.MX: Add i.MX8MM EVK board supportSascha Hauer2020-02-191-0/+10
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8M: Add i.MX8MM supportSascha Hauer2020-02-1913-25/+215
| | | | | | | | | | | | | | | | | | This adds support for the i.MX8MM. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8M: Add TF-A loading support for i.MX8MMSascha Hauer2020-02-193-10/+27
| | | | | | | | | | | | | | | | | | | | | Basically the same as for i.MX8MQ, just some function split up needed to account for different base addresses for the TF-A on both SoCs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8M: Add DDR controller supportSascha Hauer2020-02-194-158/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DDR driver for the i.MX8MQ/i.MX8MM. It's taken from U-Boot v2020.04-rc1 with slight modifications for barebox The i.MX8MQ boards in the tree currently use the output of an earlier version of the NXP i.MX8M DDR Tool which doesn't use a controller driver but instead does most stuff in board code. It seems this can coexist with the new driver, only a few helper functions that previously lived in arch/arm/mach-imx/imx8-ddrc.c are now provided by the new driver. Tested on an i.MX8MM EVK Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8M: Add and use function for early UART clock setupSascha Hauer2020-02-192-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | The i.MX8M boards all have the same code for setting up the UART clock. Add a common helper for it. In the helper just setup the clocks for all UARTs as it's not worth it to have separate functions for each UART. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX7: Add and use function for early UART clock setupSascha Hauer2020-02-191-0/+12
| | | | | | | | | | | | | | | | | | | | | The i.MX7 boards have the same code for setting up the UART clock. Add a common helper function for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8M: Add some lowlevel clock functionsSascha Hauer2020-02-192-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | U-Boot has some lowlevel clock functions which take a clock slice index as argument. Add them for barebox as well to make the code better comparable to U-Boot. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8M: rename imx8-ccm-regs.h to imx8m-ccm-regs.hSascha Hauer2020-02-191-0/+0
| | | | | | | | | | | | | | | | | | | | | i.MX8 is something different than the i.MX8M and both will not share this header file, so rename it to imx8m-ccm-regs.h Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | Add some CCM defines for i.MX8MSascha Hauer2020-02-191-2/+23
| | | | | | | | | | | | | | | | | | | | | This adds some clock slice indices and CCGR defines needed for the lowlevel i.MX8M code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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