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* ARM: layerscape: ppa: Fix use after freeSascha Hauer2020-11-111-0/+1
| | | | | | | | | | | | In of_psci_do_fixup() we want to delete the one job-ring device node which is used by the PPA secure firmware. When we have deleted the node we may not continue the for_each_compatible_node_from() loop, because that would derefence the just deleted node. We only want to delete a single node, so we do not need to continue the loop once we've found the node, so we can fix the issue by breaking out of the loop. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/percent_pe' into masterSascha Hauer2020-10-141-3/+2
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| * vsprintf: retire strerrorp in favor of %peAhmad Fatoum2020-09-291-3/+2
| | | | | | | | | | | | | | | | | | strerrorp() is only used along with printf. We now have a format specifier for printing error pointers directly, so use that and remove strerrorp. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: layerscape: ppa: fix wrong return values on some errorsAhmad Fatoum2020-10-021-1/+1
|/ | | | | | | | Coccinelle detected that the IS_ERR and ERR_PTR are mismatched. Fix it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: layerscape: ppa: fix error propagation in ppa_init()Ahmad Fatoum2020-07-141-4/+3
| | | | | | | | On fit_open_image, we returned PTR_ERR(fit) instead of the correct ret. We also didn't call fit_close as we should. Fix this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: Be less noisy when no iommu node foundSascha Hauer2020-03-241-2/+4
| | | | | | | The IOMMU node is not present in the upstream dts files. Do not complain too loudly when we are presented such a device tree. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: setup icids for the IOMMUSascha Hauer2020-01-131-16/+265
| | | | | | | | | | | | The Isolation Context Identifiers (icid) have to be configured in the hardware and communicated to the Kernel via device tree fixups. This adds the missing bits and pieces to make the IOMMU work under Linux. As of Linux-5.5 the SMMU doesn't work out of the box. This series has been tested in conjunction with this Kernel series: https://lore.kernel.org/patchwork/cover/997994/ Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* include/soc/fsl: Make struct ccsr_qman v3 specificSascha Hauer2020-01-131-1/+1
| | | | | | | | | | struct ccsr_qman is ifdeffed for different versions of this structure. CONFIG_SYS_FSL_QMAN_V3 is not defined which means we happen to use the wrong version on LS1046a. Hardcode it to the v3 version to make it work on LS1046a and rename it to ccsr_qman_v3 to make it obvious that it needs a change on non v3 versions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: replace overcomplicated macrosSascha Hauer2020-01-131-138/+204
| | | | | | | The icid tables are generated with several macros which makes the code hard to read. Drop the macros. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/randfixes'Sascha Hauer2019-12-102-2/+5
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| * ARM: layerscape: ppa: use sync_for_execution instead of a manual cache flushLucas Stach2019-12-021-2/+2
| | | | | | | | | | | | | | | | The copied code is then jumped to, so we need to sync the caches for execution instead of just flushing the data caches. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: layerscape: add missing selects for TQMLS1046ALucas Stach2019-12-021-0/+3
| | | | | | | | | | | | | | | | Make sure that all the lowlevel components are selected when only this board is built. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Layerscape: PPA: Disable CAAM JR used by secure firmwareSascha Hauer2019-11-281-0/+19
|/ | | | | | | JR3 is used by the secure firmware. We have to remove the node from the Linux device tree to prevent Linux from using it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: add bootm handler for imagesAhmad Fatoum2019-09-182-0/+59
| | | | | | | | | | The layerscape images are preceeded by a RCW and PBI, which are interpreted by the Layerscape Hardware Pre-Bootloader and aren't executable as ARM code. To maintain the ability to network boot them, add a bootm handler that skips the fixed-size header. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: Add PPA firmware supportSascha Hauer2019-05-135-0/+172
| | | | | | | | | | | The "Primary Protected Application" (PPA) is a PSCI compliant firmware distributed by NXP. It is needed to start the secondary cores on Layerscape SoCs. Without it Linux will be started in EL3 and doesn't work properly. The precompiled firmware images can be found on https://github.com/NXP/qoriq-ppa-binary and are not included in barebox. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: introduce sync_caches_for_executionSascha Hauer2019-05-131-1/+2
| | | | | | | | | | | | | | | | | | | We have several places in the code which which prepares just modified code for execution. This is done differently in all the places, so add a common function to be used by all. Most places called arm_early_mmu_cache_flush(). This function includes invalidating the instruction cache, so doing it again is unnecessary. Sometimes we had arm_early_mmu_cache_flush() inside #ifdef CONFIG_MMU. The ifdef seems unnecessary since we do not have it consistently, so remove the ifdef. Some early i.MX xload code had icache_invalidate() but forgot to flush the caches. Replace the instruction cache invalidation with sync_caches_for_execution(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: ls1046a: Add bbu handlersSascha Hauer2019-05-101-0/+22
| | | | | | | The barebox images can simply be written to the partitions, so we can use bbu_register_std_file_update() for updating to MMC and QSPI. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: ls1046a: Add automatic bootsource detection xload functionSascha Hauer2019-05-103-1/+27
| | | | | | | Add a helper function which continues booting from the detected boot source. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: Add QSPI boot supportSascha Hauer2019-05-103-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting Layerscape from QSPI is a bit tricky and the approach we take is different from the one U-Boot has taken, so it's worth writing and reading the following explanation. The QSPI controller can map the Flash contents into the memory space (On LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this memory window. The Layerscape SoCs have a PowerPC history, so it seemed appropriate for the designers to let the QSPI controller operate in big endian mode by default. To let the SoC see the correct RCW we have to write the RCW and PBI data with be64 endianess. Our PBL image tool pokes the initial binary into the SoC internal SRAM using PBI data as done with SD/MMC boot aswell. barebox then changes the QSPI controller endianess to le64 to properly read the barebox binary (placed at an flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and jumps to it. U-Boot has another approach. Here the initial binary is executed in place directly at 0x40100000. This means the QSPI controller endianess must be swapped inside the PBI data. This has the effect that the whole RCW/PBI data must be 64bit endianess swapped *except* the very last word of the PBI data which contains the CRC command and is read already with changed endianess. As a conclusion when porting QSPI PBI files from U-Boot to barebox skip commands changing the endianess in the QSPI controller and make sure the image is executed in internal SRAM and not in the Flash memory window. Lines like this should be removed: 09550000 000f400c This sets the binary execution address: 09570604 40100000 For barebox it should be changed to 0x10000000. As a result the PBI files can probably be unified between SD and QSPI boot. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: ls1046a: Add bootsource detection supportSascha Hauer2019-05-103-0/+42
| | | | | | Not much to do, there are only a few boot sources supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: Add TQ TQMLS1046a board supportSascha Hauer2019-03-131-0/+4
| | | | | | | | | | | | | This adds support for the TQ TQMLS1046a board. Currently supported: - UART - SD/MMC - Network on eth3, eth2 currently not working for unknown reasons First stage support exists but is currently untested. Serdes ports are not yet supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: Add LS1046a RDB board supportSascha Hauer2019-03-131-0/+9
| | | | | | | | | | | | | | The RDB is the Freescale LS1046a reference board. This patch adds support for it. Currently supported: - DDR4 RAM as read from SPD EEPROM - UART - SD/MMC - RGMII network ports The Serdes ports are currently not supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Add basic Layerscape supportSascha Hauer2019-03-1310-0/+769
| | | | | | | | | | This adds basic Layerscape support: - Makefile/Kconfig - Register maps - errata workarounds Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* esdhc-xload: Add support for LayerscapeSascha Hauer2019-03-131-0/+6
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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