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* Merge branch 'for-next/layerscape'Sascha Hauer2024-01-2314-149/+1164
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| * ARM: layerscape: enable DWC3 snooping on ls1046aAhmad Fatoum2024-01-111-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SCFG_SNPCNFGCR USB bits only have an effect if the Layerscape-specific bits in each DWC instance's GSBUSCFG0 are appropriately configured. As the LS1046's kernel DT is configured to assume the whole SoC is dma-coherent, we need to set these bits, so this is indeed the case. This configuration is likewise applicable to the LS1043A, should we add support for it and to the newly added LS1028A, if we start configuring the CCI-400 to make the fully cache-coherent, but alas, that's not yet the case and the LS1028A's kernel DT doesn't assume it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240110160112.4134162-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: layerscape: configure all DMA masters to be cache-coherentAhmad Fatoum2024-01-111-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upstream device tree now has /soc/dma-coherent, which breaks USB in Linux v6.1 when kernel is booted with barebox. Fix this by: - setting the snoop bits for the DMA masters, so we properly support Linux >= v6.1 DTs - fixing up cache coherency setting into kernel DT whenever barebox DT has /soc/dma-coherent to support older device trees The latter is done automatically when OF_DMA_COHERENCY is selected, so add the missing snoop bits here. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240110160112.4134162-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: add basic support for NXP LS1028a RDBSascha Hauer2024-01-101-2/+13
| | | | | | | | | | | | | | | | The NXP LS1028a RDB is a LS1028a Eval board. Currently supported are SD/MMC, ethernet and SD image generation. Link: https://lore.barebox.org/20240109161527.3237581-22-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: LS1028a: implement bootsource detectionSascha Hauer2024-01-102-0/+41
| | | | | | | | | | | | | | | | Detecting the bootsource is just a matter of decoding the porsr1 register. Implement it. Link: https://lore.barebox.org/20240109161527.3237581-19-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: LS1028a: fixup icidsSascha Hauer2024-01-102-0/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA operations from peripherals have a stream id attached to them which must match the stream ids configured in the IOMMU. Configure the stream ids in the peripheral registers and fixup the Kernel device tree with the configured stream ids. The code is based on the corresponding U-Boot code as of U-Boot-2023.10-rc1. The result is hard to match against the U-Boot code though as U-Boot hides the initialisation arrays behind multiply layered defines which are dropped here to make the code readable. Link: https://lore.barebox.org/20240109161527.3237581-12-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: icid: factor out setup_icid_offsets()Sascha Hauer2024-01-101-7/+16
| | | | | | | | | | | | | | | | | | The code to iterate over the icid table writing register values can be re-used for upcomin LS1028a support, so move the code to a separate function. Link: https://lore.barebox.org/20240109161527.3237581-10-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: icid: use of_property_write_u32_array() in ↵Sascha Hauer2024-01-101-9/+9
| | | | | | | | | | | | | | | | | | | | of_set_qportal_iommu_prop() Use of_property_write_u32_array() rather than of_set_property() to make the code a bit clearer. Link: https://lore.barebox.org/20240109161527.3237581-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: icid: use of_property_write_u32_array() in of_set_iommu_prop()Sascha Hauer2024-01-101-5/+5
| | | | | | | | | | | | | | | | Use of_property_write_u32_array() rather than of_set_property() to make the code a bit clearer. Link: https://lore.barebox.org/20240109161527.3237581-8-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: icid: move re-usable code to separate functionsSascha Hauer2024-01-101-41/+57
| | | | | | | | | | | | | | | | Create separate functions from code that can be re-used by upcoming LS1028a support. Link: https://lore.barebox.org/20240109161527.3237581-7-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: icid: rename functionsSascha Hauer2024-01-101-11/+11
| | | | | | | | | | | | | | | | We are working on unflattened trees, so use the more appropriate function prefix "of_" rather than "fdt_" Link: https://lore.barebox.org/20240109161527.3237581-6-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: icid: make readonly arrays constSascha Hauer2024-01-101-9/+9
| | | | | | | | | | | | | | | | | | Several arrays used in icid.c are statically initialised and not modified during runtime. Also they are only used locally, so make them static const. Link: https://lore.barebox.org/20240109161527.3237581-5-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: LS1028a: reserve DDR region for TF-ASascha Hauer2024-01-101-0/+22
| | | | | | | | | | | | | | | | On LS1028a the TF-A is placed in DDR, so we have to reserve the region in order to keep Linux away from it. Link: https://lore.barebox.org/20240109161527.3237581-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: consolidate initcalls into oneSascha Hauer2024-01-106-32/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | For Layerscape we have multiple initcalls in the arch directory. Consolidate these into one initcall which detects the SoC type once and calls the appropriate init functions. This makes it easier to add future init steps and also we reduce the number of string comparisons. For added value also cpu_is_ls10xx() functions are added which might become in handy later. Link: https://lore.barebox.org/20240109161527.3237581-3-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add ls1028a lowlevel initSascha Hauer2024-01-082-0/+44
| | | | | | | | | | Link: https://lore.barebox.org/20240104141746.165014-16-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: add tzc400 supportSascha Hauer2024-01-083-0/+468
| | | | | | | | | | | | | | | | | | | | This adds the code necessary to initialize the TZC400 unit found on the LS1028a. The code is taken from TF-A. It's mostly SoC independent, but keep it in arch-layerscape for now until we get a second user and it's clear which parts can be re-used. Link: https://lore.barebox.org/20240104141746.165014-15-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: layerscape: implement ls1028a errataSascha Hauer2024-01-081-0/+49
| | | | | | | | | | Link: https://lore.barebox.org/20240104141746.165014-12-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: pass base addresses to errata functionsSascha Hauer2024-01-081-15/+8
| | | | | | | | | | Link: https://lore.barebox.org/20240104141746.165014-10-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: layerscape: cleanup erratum_a009008Sascha Hauer2024-01-081-2/+3
| | | | | | | | | | | | | | | | | | Drop generic erratum_a00i9008_layerscape() and move its implementation into the SoC specific pendants to make the way free for more SoC support. Link: https://lore.barebox.org/20240104141746.165014-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: layerscape: drop wrong errata workaroundSascha Hauer2024-01-081-8/+0
| | | | | | | | | | | | | | | | | | | | set_usb_txvreftune() works on the USB Parameter 1 Control Register. USB Parameter 2 Control Register has a different register layout and calling set_usb_txvreftune() on it is wrong. Drop the bogus errata workaround. Link: https://lore.barebox.org/20240104141746.165014-8-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: layerscape: cleanup erratum_a009798Sascha Hauer2024-01-081-2/+3
| | | | | | | | | | | | | | | | | | Drop generic erratum_a009798_layerscape() and move its implementation into the SoC specific pendants to make the way free for more SoC support. Link: https://lore.barebox.org/20240104141746.165014-7-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: layerscape: cleanup erratum_a008997Sascha Hauer2024-01-081-2/+3
| | | | | | | | | | | | | | | | | | Drop generic erratum_a008997_layerscape() and move its implementation into the SoC specific pendants to make the way free for more SoC support. Link: https://lore.barebox.org/20240104141746.165014-6-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: layerscape: cleanup erratum_a009007Sascha Hauer2024-01-081-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | Drop the generic erratum_a009007_layerscape() function and move the code into its SoC specific pendants to make the way free for additional SoCs. While at it remove the USB_PHY_RX_EQ_VAL_x defines from immap_lsch2.h to get rid of conflicting defines in that file. Link: https://lore.barebox.org/20240104141746.165014-5-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: layerscape: decide SCFG endianess during runtimeSascha Hauer2024-01-085-4/+62
| | | | | | | | | | | | | | | | SCFG endianess differs between SoCs. Currently supported SoCs have a big endian SCFG unit, but upcoming LS1028a support has a little endian SCFG. Link: https://lore.barebox.org/20240104141746.165014-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * soc/fsl/immap_lsch2.h: cleanupSascha Hauer2024-01-081-0/+5
| | | | | | | | | | | | | | | | Some values differ between LS1046a and LS1021. Move them directly where needed so that we can drop the #ifdef SOC_TYPE from immap_lsch2.h Link: https://lore.barebox.org/20240104141746.165014-3-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: layerscape: ppa: fix type of C variable used in inline assemblyAhmad Fatoum2024-01-101-1/+1
|/ | | | | | | | | | | clang warns that cr should be an unsigned long as it's used to initialize a register argument for the mrs instruction. Change the type from unsigned int to unsigned long to fix this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240108095959.1249068-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: layerscape: ppa: Enable MMU when in EL2Sascha Hauer2023-11-271-0/+7
| | | | | | | We enter EL2 with MMU disabled even when it was enabled in EL3. Enable MMU in EL2 again. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: layerscape: ppa: Fix starting PPASascha Hauer2023-11-211-9/+9
| | | | | | | | | | | | | | With dba1c26f70 we replaced request_sdram_region() for the PPA with reserve_sdram_region(). The effect is that the region is marked as reserved and mapped non executable. While this is desired for EL2, it also has the effect that we can't start the PPA anymore from EL3. Map the region cached/executable to start the PPA, then map it uncached/non executable once we are in EL2. Fixes: dba1c26f70 ("arm: layerscape: ppa: reserve SDRAM region for PPA") Link: https://lore.barebox.org/20231120144453.1075740-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: layerscape: ppa: Add PPA as /reserved-memory/ppa nodeSascha Hauer2023-10-191-1/+1
| | | | | | | | | Instead of adding a /memreserve/ entry, add the PPA as a /reserved-memory/ppa node. For the Kernel it doesn't make a difference, but using a node makes the range visible in /sys/firmware/devicetree and the node name also gives a hint what the region is reserved for. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: layerscape: ppa: reserve SDRAM region for PPASascha Hauer2023-10-191-1/+1
| | | | | | | | | The region the PPA is stored may not be speculated into by the CPU. We have reserve_sdram_region() for this purpose. With this the region is mapped uncached with excute never bit set. Use this rather than request_sdram_region(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2023-04-191-1/+8
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| * ARM: cleanup 32bit/64bit support in KconfigSascha Hauer2023-04-051-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The decision whether to build a 32bit or 64bit barebox has to be made first before anything else, so this makes CONFIG_64BIT a toplevel option without any further dependencies. With this patch we will only present the SoCs/boards which are actually supported by the selected code model in Kconfig. Without this patch it was often possible to select 32bit boards on a 64bit build or vice versa, which resulted in a broken build. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: LS1021A: slow bootRenaud Barbier2023-04-111-0/+4
|/ | | | | | | | | | It was noticed that the LS1021A-IOT was slow to boot and perform computing intensive operations. Enable SMP so the cortex-a7 cache works as expected. Signed-off-by: Renaud Barbier mailto:renaud.barbier@ametek.com Link: https://lore.barebox.org/BL0PR07MB5665E8DA118845ED96A8289DEC959@BL0PR07MB5665.namprd07.prod.outlook.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: Add LS1021A IOT board supportRenaud Barbier2023-03-151-4/+0
| | | | | | | | | | | | | The LS1021A-IOT is a NXP reference board. Currently supported: - DDR3 RAM fixed settings - UART - SPI boot Signed-off-by: Renaud Barbier <renaud.barbier@ametek.com> Link: https://lore.barebox.org/BL0PR07MB5665D0F82835E5C29AA0B13BECB99@BL0PR07MB5665.namprd07.prod.outlook.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: add LS1021A to Layerscape machine supportRenaud Barbier2023-03-159-30/+623
| | | | | | | | | | | | | This updates the Layerscape support in preparation for the introduction of the LS1021A-IOT: - Makefile/Kconfig - LS1021A specific register maps and configurations - errata workarounds update Signed-off-by: Renaud Barbier <renaud.barbier@ametek.com> Link: https://lore.barebox.org/BL0PR07MB56654DCD4F18A3B1A6A2F2E4ECB99@BL0PR07MB5665.namprd07.prod.outlook.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: layerscape: Move mach header files to include/mach/layerscapeSascha Hauer2023-03-0612-121/+10
| | | | | | | | | | Currently arch specific headers can be included with longer possible as there won't be a single mach anymore. Move all layerscape specific header files to include/mach/layerscape/ to prepare for multi-arch support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: psci: make PSCI method a of_psci_fixup parameterAhmad Fatoum2022-11-071-1/+1
| | | | | | | | | | | | | | We currently assume PSCI fixups to always be of method smc, but this is not true when barebox fixes up the node while running under QEMU. In preparation for handling QEMU boot properly when psci-client driver is enabled, give of_psci_fixup an extra parameter. No functional change. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20221105121154.3716964-1-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* bootsource: rename existing bootsource_set to bootsource_set_rawAhmad Fatoum2022-08-091-2/+2
| | | | | | | | | | | | | | | | | Patterns like [ "$bootsource" = mmc ] && boot mmc$bootsource_instance expect that ${bootsource_instance} and MMC aliases align, which may not always be the case. In preparation for adding a new bootsource_set function that consults an optional mapping table from bootrom bootsource_instance to board-specific device numbering, rename all existing instances to bootsource_set_raw. While at it, clean up the legacy split into bootsource_set and bootsource_set_instance and have the new bootsource_set_raw accept both arguments at once. No functional change intended. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220720055042.3510276-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: cpu: remove unnecessary CONFIG_SYS_SUPPORTS_64BIT_KERNELAhmad Fatoum2022-06-171-1/+0
| | | | | | | | | | For ARM, SYS_SUPPORTS_64BIT_KERNEL is selected exclusively by symbols that also select CPU_SUPPORTS_64BIT_KERNEL, so we can drop SYS_SUPPORTS_64BIT_KERNEL safely. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220609055922.667016-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: cpu: prevent recursive dependencies via CPU_SUPPORTS_64BIT_KERNELAhmad Fatoum2022-06-171-0/+1
| | | | | | | | | | | | | For ARM, CONFIG_CPU_SUPPORTS_64BIT_KERNEL's only function, along with CONFIG_SYS_SUPPORTS_64BIT_KERNEL is to control visibility of the 64BIT symbol. Select it from CPU_V8 is detrimental, because subarches may want to select CPU_SUPPORTS_64BIT_KERNEL unconditionally and select CPU_V8 only if 64BIT was chosen. This currently leads to a recursive dependency, so break this up. No functional change just yet. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220609055922.667016-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arch: add SPDX-License-Identifier to all .c filesAhmad Fatoum2022-01-052-0/+4
| | | | | | | | | Record GPL-2.0-only as license for all files lacking an explicit license statement. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arch: add SPDX-License-Identifier to all .S filesAhmad Fatoum2022-01-052-0/+4
| | | | | | | | | Record GPL-2.0-only as license for all files lacking an explicit license statement. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-10-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arch: add SPDX-License-Identifier to all headersAhmad Fatoum2022-01-056-1/+13
| | | | | | | | | Record GPL-2.0-only as license for all files lacking an explicit license statement. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-9-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: add SPDX-License-Identifier for Kbuild/KconfigAhmad Fatoum2022-01-052-0/+4
| | | | | | | | | | | | | | | To verify only Kconfig/Makefile is touched: git show --numstat --format=oneline HEAD | grep -v 'Kconfig\|Makefile' will print only arch/powerpc/Kbuild. To verify nothing unexpected is added: git show -U0 | grep '^-[^-]\|^+[^+]' | sort -u Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: layerscape: Fix wrong error checkSascha Hauer2021-05-181-2/+2
| | | | | | | | | | The return value of get_fman_port_icid() is assigned to an unsigned variable which is then error checked for being smaller than 0. Convert the variable to a signed type to make this work. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210517185424.32145-10-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: layerscape: ppa: Fix use after freeSascha Hauer2020-11-111-0/+1
| | | | | | | | | | | | In of_psci_do_fixup() we want to delete the one job-ring device node which is used by the PPA secure firmware. When we have deleted the node we may not continue the for_each_compatible_node_from() loop, because that would derefence the just deleted node. We only want to delete a single node, so we do not need to continue the loop once we've found the node, so we can fix the issue by breaking out of the loop. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/percent_pe' into masterSascha Hauer2020-10-141-3/+2
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| * vsprintf: retire strerrorp in favor of %peAhmad Fatoum2020-09-291-3/+2
| | | | | | | | | | | | | | | | | | strerrorp() is only used along with printf. We now have a format specifier for printing error pointers directly, so use that and remove strerrorp. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: layerscape: ppa: fix wrong return values on some errorsAhmad Fatoum2020-10-021-1/+1
|/ | | | | | | | Coccinelle detected that the IS_ERR and ERR_PTR are mismatched. Fix it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: layerscape: ppa: fix error propagation in ppa_init()Ahmad Fatoum2020-07-141-4/+3
| | | | | | | | On fit_open_image, we returned PTR_ERR(fit) instead of the correct ret. We also didn't call fit_close as we should. Fix this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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