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path: root/arch/arm/mach-mvebu/armada-370-xp.c
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* ARM: mvebu: Enable PUP registerEzequiel Garcia2014-11-111-0/+5
| | | | | | | | | | | | | | As reported by Sebastian, we need to enable this explicitly for the Tx clock on RGMII. While here, let's enable all the other peripherals. Although this is documented to be required only for Armada XP SoC, it has been found to be harmless on Armada 370, so we do it unconditionally to simplify the code. Reported-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: Check for correct SoC in of_fixup callbackSascha Hauer2014-09-191-0/+3
| | | | | | | | Only run the fixup when we are actually on the corresponding SoC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: mvebu: Simplify memory init orderSascha Hauer2014-09-191-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialisation of the memory nodes on mvebu is a bit compilcated: pure_initcall(mvebu_memory_fixup_register) of_register_fixup(mvebu_memory_of_fixup, NULL) core_initcall(kirkwood_init_soc) mvebu_set_memory() core_initcall(of_arm_init) of_fix_tree() mvebu_memory_of_fixup() First a mvebu common of_fixup function is registered, then the SoC calls mvebu_set_memory which stores the memory base and size in global variables. Afterwards the of_fixup is executed which fixes the memory nodes according to the global variables. Instead register a SoC specific fixup which directly calls mvebu_set_memory with the memory base and size as arguments: pure_initcall(kirkwood_register_soc_fixup); of_register_fixup(kirkwood_init_soc, NULL); core_initcall(of_arm_init) of_fix_tree() kirkwood_init_soc() mvebu_set_memory(phys_base, phys_size); Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: Add machine compatible to mbus rangesSebastian Hesselbarth2014-09-191-1/+2
| | | | | | | | | | Multi-SoC support for MVEBU will add mbus ranges for all compiled SoCs. To protect the mbus node of the SoC barebox is executed on from others ranges, pass machine's compatible to mvebu_mbus_add_range and check before applying the fixup. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: Add common reset_cpu functionSascha Hauer2014-09-191-9/+10
| | | | | | | | | mvebu has a reset_cpu function per SoC this does not work when multiple SoCs are selected, so add a common reset_cpu function which calls into the SoC specific ones. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: mvebu: armada-370-xp: disable MBUS error propagationSebastian Hesselbarth2014-07-311-0/+6
| | | | | | | | | | Accessing MBUS windows not backed-up by e.g. PCIe devices will hang the SoC. Disable MBUS error propagation back to CPU allows to read 0xffffffff instead of hanging the SoC. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: add fixup for directly attached memorySebastian Hesselbarth2014-07-251-1/+1
| | | | | | | | | | | | On Marvell MVEBU SoCs memory size is set up by BootROM and can be read from SoC's RAM controller. With early DT fixups available, set corresponding DT node to reflect accessible amount of directly attached RAM. This patch also removes non-DT call to arm_add_mem_device to silence a warning about request_region conflict due to adding a mem device twice. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: add register remap for mbus idsSebastian Hesselbarth2014-07-251-0/+3
| | | | | | | | For each supported MVEBU SoC, add the corresponding remapped registers to fix them up in provided DTBs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: convert Armada 370/XP devices to be probed from DTSebastian Hesselbarth2014-06-241-65/+1
| | | | | | | | With Armada 370/XP DT files available, convert Armada 370/XP SoC init to register basic devices from DT only. Makefile targets for dtbs will be removed again as soon as MULTI_PBL is available. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: mvebu: add 25MHz fixed clock for Armada XPSebastian Hesselbarth2014-06-241-0/+5
| | | | | | | Armada XP timers can be run from a 25MHz fixed clock. Add the corrsponding clock and clock alias to SoC setup. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* x86: ns16550: Rework driver to allow for x86 I/O spaceMichel Stam2014-04-091-1/+2
| | | | | | | | | | | | The current implementation fakes a memory-mapped I/O device at 0x3f8 and 0x2f8, then uses platform read/write functions to do the actual reading and writing. These platform functions only exist for the x86 platform; better to move the I/O routines into the driver and have the driver request I/O ports using request_ioport_region. Signed-off-by: Michel Stam <michel@reverze.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Set model and hostname at boardlevelSascha Hauer2013-08-161-0/+3
| | | | | | | | | | | | With multiboard support the compiletime generated BOARDINFO string gets more and more meaningless. This removes it from Kconfig and replaces it with a variable that can be set at boardlevel. Also many boards have a standard setting for the hostname in the environment. This patch also moves the standard to C code by calling barebox_set_hostname(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clocksource: mvebu: lookup clock by physbaseSebastian Hesselbarth2013-07-051-1/+2
| | | | | | | | This converts Armada 370/XP SoC init to register tclk alias for timer by physbase instead of name. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: move soc_init to core_initcallSebastian Hesselbarth2013-07-051-1/+1
| | | | | | | | Clocks need to be accessed early for DT support, so move soc_init to core_initcall instead of postcore_initcall. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: mvebu: introduce common lowlevel and early initSebastian Hesselbarth2013-05-211-62/+41
| | | | | | | | | | | | | At early stage after boot, all MVEBU SoCs are similar enough to have a common lowlevel and barebox entry. We also remap the internal register base address to 0xf100000 as it gives some 512M more of contiguous address space. As we cannot determine real memory size that early, we start with a default memory size of 64M and probe correct size later in SoC init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: mach-mvebu: rename Armada 370/XP core codeSebastian Hesselbarth2013-05-151-0/+142
There are more than Armada 370/XP in Marvell MVEBU SoC familiy. To avoid irritation with source file nameing, we rename setup source file for Armada 370/XP from core.c to armada-370-xp.c. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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