summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-mvebu
Commit message (Collapse)AuthorAgeFilesLines
* mvebu: make the compiler inline mvebu_remap_registersUwe Kleine-König2019-06-071-1/+1
| | | | | | | | | | | Without that gcc 7.3.1 (from OSELAS.Toolchain-2018.02.0) makes mvebu_remap_registers a standalone function which in its prolog saves two registers to the stack. However this function is called early during startup when there is no stack available yet and sp still points into the nirvana which makes barebox crash. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: add basic support for the Armada XP DB platformSascha Hauer2019-05-071-0/+4
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: Add missing includesSascha Hauer2019-03-181-0/+1
| | | | | | | | | Many files in the tree implement functions, but do not include the header files which provide the prototypes for these functions. This means conflicting prototypes remain undetected. Add the missing includes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: Make locally used functions staticSascha Hauer2019-03-181-1/+1
| | | | | | | Many functions are only used locally but still are globally visible. Make these function static. Avoids warnings generated with -Wmissing-prototypes Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: delete unused mach/dove.hAlexander Shiyan2019-01-211-23/+0
| | | | | | | This removes the stale mach/dove.h include as there is no user of it. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: delete unused mach/kirkwood.hAlexander Shiyan2019-01-211-22/+0
| | | | | | | This removes the stale mach/kirkwood.h include as there is no user of it. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: Remove trailing whitespaces and tabsAlexander Shiyan2019-01-211-3/+3
| | | | | | | Just a cleanup over barebox tree Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mvebu: create bbu handler for kwb images and use it on cuboxUwe Kleine-König2018-06-133-0/+67
| | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kwbimage_v0: add support to detect and boot a mvebu v0 imageUwe Kleine-König2018-06-041-2/+9
| | | | | | | | | The differences between v0 and v1 of the mvebu kwbimage are small enough that the function to boot such an image can be shared between both variants. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* dove: fix bit layout of DOVE_CPU_CTRL registerUwe Kleine-König2018-05-311-2/+2
| | | | | | | | | | | | | While creating the previous patch I checked the cpu's reference manual to see what the affected registers actually do and noticed that bits of the DOVE_CPU_CTRL actually used by the code doesn't match the bits described as AHBSlaveBase in the manual. I'm not aware of any effect (neither positive nor negative) of this patch. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* dove: move memory controller remapping before RAM detectionUwe Kleine-König2018-05-312-22/+29
| | | | | | | | | | | | | | | | | | Compared to other mvebu cpus the memory controller registers are in their own register window that can be moved independently of the mbus register window. Since commit f05c6e095cf8 the available RAM configured by the boot ROM is read out earlier. This happens to be before the memory controller register window is moved and so dove_memory_find() fails. To fix this move the memory controller window together with the mbus window. This change allows to boot barebox first stage again on a Solidrun Cubox. Fixes: f05c6e095cf8 ("mvebu: rework how memory is detected") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: get_runtime_offset() returns unsigned longSascha Hauer2018-03-211-1/+1
| | | | | | | Change return type from uint32_t to unsigned long which is suitable for aarch64 aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: return positive offset in get_runtime_offset()Sascha Hauer2018-03-211-1/+1
| | | | | | | | | | | When we are linked at 0x0 and running at 0x01000000 then get_runtime_offset() should return 0x01000000 and not 0xff000000. This makes get_runtime_offset() more consistent and better understandable. This was tested on a Freescale i.MX53 Quickstart board. Additionally relocate_to_adr() was tested since that is normally not called. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: armada-xp: configure PLL and PHY registerJan Luebbe2017-08-152-0/+47
| | | | | | | | | The PLL setup is needed to use the USB ports in Linux. This code is ported from mainline U-Boot arch/arm/mach-mvebu/cpu.c. Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* ARM: mvebu: Add initial support for Turris OmniaUwe Kleine-König2017-06-191-0/+10
| | | | | | | | Up to now only 2nd stage booting is tested and boots up to a prompt. i2c and spi are working, ethernet, usb and sata don't. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: initial support for Armada 38xUwe Kleine-König2017-06-192-0/+6
| | | | | | | | This SoC is similar enough to Armada 380/XP to make use of the code supporting these without further adaption. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: fix size mask for RAM windowUwe Kleine-König2017-06-131-1/+1
| | | | | | | | | | The size field in the window control register occupies bits 31:16. So adapt ARMADA_370_XP_DDR_SIZE_MASK accordingly. This fixes detection of RAM chips smaller than 32 MiB and so probably doesn't affect any supported machine. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: only build kwbootimage support if BOOTM is enabledLucas Stach2017-03-221-1/+1
| | | | | | | | As this is the bootm image handler implementation for the kwbootimage it is of no use if BOOTM is missing and fails to link. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kwbimage_v1: add support to boot a mvebu imageUwe Kleine-König2017-03-022-0/+85
| | | | | | | | This just starts the main image of the mvebu image assuming that the header images just setup the RAM. The position of the internal register window is provided in the header as introduced in the previous commit. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* mvebu: get initial position of register window from image headerUwe Kleine-König2017-03-023-3/+74
| | | | | | | | | | | | | | | A problem when using 2nd stage booting on mvebu is that the first bootloader already switched the register window location from 0xd0000000 to 0xf1000000 by writing to 0xd0000080. When the second bootloader also tries to do this switch it writes to the wrong location resulting in an exception and so a boot failure. For this reason the base address of the register window is passed in the barebox header and picked up from there by early code. In a further patch bootm is taught to put the actual position of the window there for the second bootloader to finally make second stage booting work. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* mvebu: kirkwood: simplify soc init code flowUwe Kleine-König2017-03-021-9/+2
| | | | | | | | | | | | | | | Similar to the two previous commits, this gets rid of a of-fixup which is strange because the soc init stuff is rerun then when a new dt for booting into Linux is loaded. The initcall must be postponed to post-core to ensure of_machine_is_compatible is working correctly. The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to ensure it's registered early enough. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mvebu: dove: simplify soc init code flowUwe Kleine-König2017-03-021-11/+2
| | | | | | | | | | | | | | | Similar to the previous commit, this gets rid of a of-fixup which is strange because the soc init stuff is rerun then when a new dt for booting into Linux is loaded. The initcall must be postponed to post-core to ensure of_machine_is_compatible is working correctly. The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to ensure it's registered early enough. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mvebu: armada-370-xp: simplify soc init code flowUwe Kleine-König2017-03-021-23/+8
| | | | | | | | | | | | | | This gets rid of a of-fixup which is strange because the soc init stuff is rerun then when a new dt for booting into Linux is loaded. The initcall must be postponed to post-core to ensure of_machine_is_compatible is working correctly. The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to ensure it's registered early enough. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mvebu: rework how memory is detectedUwe Kleine-König2017-02-168-182/+124
| | | | | | | | | | | | | | Status quo is that initially a size of 64 MiB is assumed (which is also used to determine the size of the malloc area) and then later the dtb is fixed up with the actually available RAM which is then used. Instead detect the real RAM size earlier and don't fixup the device tree. The device tree is fixed up instead by generic code. This way the malloc area is more appropriately sized and RAM detection is more similar to mach-imx which is both nice. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mvebu: remove unused function barebox_arm_reset_vectorUwe Kleine-König2017-02-161-6/+0
| | | | | | | This isn't needed since mvebu was converted to multi-pbl Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mvebu: simplify detection and fixup of MV78230-A0Uwe Kleine-König2017-02-161-19/+12
| | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: add support for Netgear RN2120Uwe Kleine-König2016-10-071-0/+4
| | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Add initial support for Netgear ReadyNAS 104Uwe Kleine-König2016-01-221-0/+4
| | | | | | | | | | | | | | | Currently only second stage booting from the vendor U-Boot is tested. I don't want to flash barebox into NAND yet because UART-booting for recovery doesn't work for me. Working so far are: - UART - networking - nand flash Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* restart: replace reset_cpu with registered restart handlersSascha Hauer2015-08-275-26/+15
| | | | | | | | | | | | | | | | | | | | | | This replaces the reset_cpu() function which every SoC or board must provide with registered handlers. This makes it possible to have multiple reset functions for boards which have multiple ways to reset the machine. Also boards which have no way at all to reset the machine no longer have to provide a dummy reset_cpu() function. The problem this solves is that some machines have external PMICs or similar to reset the system which have to be preferred over the internal SoC reset, because the PMIC can reset not only the SoC but also the external devices. To pick the right way to reset a machine each handler has a priority. The default priority is 100 and all currently existing restart handlers are registered with this priority. of_get_restart_priority() allows to retrieve the priority from the device tree which makes it possible for boards to give certain restart handlers a higher priority in order to use this one instead of the default one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: armada-xp: Add Lenovo Iomega ix4-300dSebastian Hesselbarth2015-04-271-0/+4
| | | | | | | | This adds support for Marvell Armada XP based 4-bay NAS Lenovo Iomega ix4-300d. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: armada-xp: Sort boards and images alphabeticallySebastian Hesselbarth2015-04-271-4/+4
| | | | | | | | Before adding new Armada XP based boards becomes messier than necessary, sort Armada XP based board Kconfig and image Makefile alphabetically. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: armada-xp: Use MBUS_ERR_PROP_EN defineSebastian Hesselbarth2015-04-271-3/+3
| | | | | | | | With proper defines for ARMADA_370_XP_FABRIC_CTRL and MBUS_ERR_PROP_EN make use of it. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: armada-xp: Limit PUP access to Armada XPSebastian Hesselbarth2015-04-272-6/+15
| | | | | | | | | | | | | | Commit 6638760c225c37f90e822ebf4dd8f0d2cd0b0ef3 ("ARM: mvebu: Enable PUP register") correctly enables devices that are disabled after boot-up due to some Design For Testability registers. However, although harmless on Armada 370, call the code conditionally on Armada XP only. While at it, move PUP register defines to SYSCTL registers where they belong to. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: armada-xp: Fixup broken MV78230-A0 SoC IDSebastian Hesselbarth2015-04-272-4/+86
| | | | | | | | | Marvell Armada XP MV78230-A0 incorrectly identifies itself as MV78460. Check number of CPUs in FABRIC_CONF and fixup PCIe DEV_ID when it is 2 CPUs instead of 4. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: Move PCIe register defines to socid.hSebastian Hesselbarth2015-04-272-4/+5
| | | | | | | | To prepare PCIe device id fixups, move PCIe register defines to a common location. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* bus: mvebu-mbus: Convert mbus platform driver to direct driverSebastian Hesselbarth2015-04-273-0/+3
| | | | | | | | | | Registering mbus driver as platform driver is a little late for some register accesses to work. We have to make sure boot-up mbus windows are disabled early, so call mbus driver directly from SoC init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sizes.h: move include/sizes.h to include/linux/sizes.hMasahiro Yamada2015-01-081-1/+1
| | | | | | | | | | | | | | This file originates in Linux. Linux has it under include/linux/ directory since commit dccd2304cc90. Let's move it to the same place as well in barebox. This commit was generated by the following commands: find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:' git mv include/sizes.h include/linux/ Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: Enable PUP registerEzequiel Garcia2014-11-112-0/+12
| | | | | | | | | | | | | | As reported by Sebastian, we need to enable this explicitly for the Tx clock on RGMII. While here, let's enable all the other peripherals. Although this is documented to be required only for Armada XP SoC, it has been found to be harmless on Armada 370, so we do it unconditionally to simplify the code. Reported-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2014-10-021-4/+0
|\
| * pinctrl: fix Kconfig dependenciesSascha Hauer2014-09-151-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove OFDEVICE dependency from PINCTRL. It won't do much then, so add a comment to Kconfig when PINCTRL is selected without OFDEVICE - Let Architectures only select PINCTRL instead of the particular driver. Change the drivers to 'default y if $SOC' to make sure the drivers are still compiled if the corresponding SoC is selected This fixes Kconfig warnings like: warning: (PINCTRL_ARMADA_370 && PINCTRL_ARMADA_XP && PINCTRL_DOVE && PINCTRL_KIRKWOOD) selects PINCTRL which has unmet direct dependencies (OFDEVICE) Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* | ARM: mvebu: Allow multiple SoCsSascha Hauer2014-09-231-21/+15
| | | | | | | | | | | | | | | | Now that the correct SoC specific memory fixup function is called we can allow to select multiple SoCs in Kconfig. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* | ARM: mvebu: Check for correct SoC in of_fixup callbackSascha Hauer2014-09-193-0/+9
| | | | | | | | | | | | | | | | Only run the fixup when we are actually on the corresponding SoC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* | ARM: mvebu: Simplify memory init orderSascha Hauer2014-09-195-37/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialisation of the memory nodes on mvebu is a bit compilcated: pure_initcall(mvebu_memory_fixup_register) of_register_fixup(mvebu_memory_of_fixup, NULL) core_initcall(kirkwood_init_soc) mvebu_set_memory() core_initcall(of_arm_init) of_fix_tree() mvebu_memory_of_fixup() First a mvebu common of_fixup function is registered, then the SoC calls mvebu_set_memory which stores the memory base and size in global variables. Afterwards the of_fixup is executed which fixes the memory nodes according to the global variables. Instead register a SoC specific fixup which directly calls mvebu_set_memory with the memory base and size as arguments: pure_initcall(kirkwood_register_soc_fixup); of_register_fixup(kirkwood_init_soc, NULL); core_initcall(of_arm_init) of_fix_tree() kirkwood_init_soc() mvebu_set_memory(phys_base, phys_size); Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mvebu: Add machine compatible to mbus rangesSebastian Hesselbarth2014-09-193-4/+8
| | | | | | | | | | | | | | | | | | | | Multi-SoC support for MVEBU will add mbus ranges for all compiled SoCs. To protect the mbus node of the SoC barebox is executed on from others ranges, pass machine's compatible to mvebu_mbus_add_range and check before applying the fixup. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: mvebu: Add common reset_cpu functionSascha Hauer2014-09-195-28/+46
|/ | | | | | | | | mvebu has a reset_cpu function per SoC this does not work when multiple SoCs are selected, so add a common reset_cpu function which calls into the SoC specific ones. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: mvebu: Add Plat'home's Kirkwood Openblocks A6 board supportEzequiel Garcia2014-09-011-0/+3
| | | | | | | | | This commit adds a new Marvell Kirkwood-based board, by following the currently supported boards. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: armada-370-xp: disable MBUS error propagationSebastian Hesselbarth2014-07-312-0/+8
| | | | | | | | | | Accessing MBUS windows not backed-up by e.g. PCIe devices will hang the SoC. Disable MBUS error propagation back to CPU allows to read 0xffffffff instead of hanging the SoC. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: add fixup for directly attached memorySebastian Hesselbarth2014-07-255-3/+64
| | | | | | | | | | | | On Marvell MVEBU SoCs memory size is set up by BootROM and can be read from SoC's RAM controller. With early DT fixups available, set corresponding DT node to reflect accessible amount of directly attached RAM. This patch also removes non-DT call to arm_add_mem_device to silence a warning about request_region conflict due to adding a mem device twice. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: add register remap for mbus idsSebastian Hesselbarth2014-07-253-0/+10
| | | | | | | | For each supported MVEBU SoC, add the corresponding remapped registers to fix them up in provided DTBs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pinctrl: mvebu: add pinctrl driver for Armada XPSebastian Hesselbarth2014-07-231-0/+1
| | | | | | | | | This adds a pinctrl driver for pin muxing on Marvell Armada XP. The driver is ported from Linux and modified to fit on Barebox's common mvebu pinctrl driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-24 03:11:18 +0000