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* arm: am33xx: Initialize EMIF REG_PR_OLD_COUNTDaniel Schultz2017-01-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on a patch from the U-Boot and fixes two errors with the LCDC. Original commit message from Jyri Sarha [1]: "Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock." The register values are generated by testing, because there is no formula to calculate them. Also from Jyri Sarha [1]: "In practice the only rule to find an optimal value is to find as high as possible REG_PR_OLD_COUNT value that does not produce LCDC FIFO underflows under worst case scenario. The worst case happens when the highest pixel clock videomode with maximum bpp is used while memory subsystem is stressed by endless stream of writes hitting the same memory memory bank (can be the same address)." It only contains the BeagleBone Black and the Phytec SoM, because I don't have other boards. [1] https://patchwork.ozlabs.org/patch/704013/ Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: am33xx: add reset duration control register address definitionYegor Yefremov2017-01-101-0/+1
| | | | | | | | PRM_RSTTIME register provides settings for global and power domain reset durations. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* OMAP: am33xx_bbu_nand: Extent barebox update handlerTeresa Remmet2016-06-301-2/+5
| | | | | | | | Make it possible to write barebox image to multiple partitions like xload partitions. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* OMAP: xload: nand: Check for redundant barebox partitionTeresa Remmet2016-06-301-0/+2
| | | | | | | | Add a support for a redundant barebox backup partition if loading barebox image from first barebox partitions fails. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: omap_gpmc: Remove BCH4 supportTeresa Remmet2016-04-121-1/+0
| | | | | | | This has no users and seems to be untested. Removed it. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: am33xx: Master Osc clock speed handlingDaniel Schultz2016-01-261-1/+1
| | | | | | | | | Setup the plls with Master Osc. clock speed from the SYSBOOT Configuration Pin. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: am33xx: Move function to read from Master OSCDaniel Schultz2016-01-261-0/+1
| | | | | | | | | Move the function to read the Master OSC speed from the SYSBOOT Configuration Pin for reuse. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Omap3: Remove useless inlineSascha Hauer2015-12-101-1/+1
| | | | | | | | | | Silences gcc5 warning: In file included from arch/arm/mach-omap/gpmc.c:31:0: arch/arm/mach-omap/include/mach/sys_info.h:93:83: warning: inline function 'get_sysboot_value' declared but never defined Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: am33xx: Add barebox_update eMMC optionDaniel Schultz2015-09-091-0/+18
| | | | | | | | | | | | | | | | | | | | | With this patch the barebox_update command will be extended by the possibility to flash the MLO to eMMC devices. The MLO will be flashed to the following addresses: 0x00000 0x20000 0x40000 0x60000 Because the first 512 Bytes of the MLO are reserved for the CHSETTINGS header and this only use ~80 Bytes, there is space for the partition table in the header. The command will overwrite the bootstrap code area and will hold the partition table and the Boot signature. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* restart: replace reset_cpu with registered restart handlersSascha Hauer2015-08-273-6/+0
| | | | | | | | | | | | | | | | | | | | | | This replaces the reset_cpu() function which every SoC or board must provide with registered handlers. This makes it possible to have multiple reset functions for boards which have multiple ways to reset the machine. Also boards which have no way at all to reset the machine no longer have to provide a dummy reset_cpu() function. The problem this solves is that some machines have external PMICs or similar to reset the system which have to be preferred over the internal SoC reset, because the PMIC can reset not only the SoC but also the external devices. To pick the right way to reset a machine each handler has a priority. The default priority is 100 and all currently existing restart handlers are registered with this priority. of_get_restart_priority() allows to retrieve the priority from the device tree which makes it possible for boards to give certain restart handlers a higher priority in order to use this one instead of the default one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: OMAP: AM33xx: add uart1 pinmux setupMichael Grzeschik2015-07-241-0/+1
| | | | | Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: am335x: Changed timerDaniel Schultz2015-07-201-0/+4
| | | | | | | | | The 32KHz from dmtimer0 is derived from a SoC internal RC oscillator which is quite inaccurate. Switch to dmtimer2 which is driven from the high frequency oscillator clock. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/omap'Sascha Hauer2015-07-032-1/+3
|\ | | | | | | | | Conflicts: arch/arm/boards/beagle/board.c
| * ARM: OMAP: Add omap3 USB loader toolSascha Hauer2015-07-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The OMAP3 supports uploading the first stage bootloader via USB. The ROM leaves the MUSB controller enabled and it can then be used to upload a 2nd stage image. This patch adds the omap3-usb-loader tool and the necessary barebox support to upload the 2nd stage image. The omap usb loader tool is downloaded from https://github.com/grant-h/omap_loader and changed to also accept CHSETTINGS images. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: OMAP3: Change DSS divider to the one U-Boot usesSascha Hauer2015-07-021-1/+1
| | | | | | | | | | | | | | | | | | U-Boot uses 2 as the DSS divider, so do the same in barebox. This shouldn't currently have any effect to barebox, but makes porting some U-Boot code easier which makes assumptions about the DSS clock rate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: AM335x: replace specific barebox update handler with generic oneSascha Hauer2015-07-011-3/+2
|/ | | | | | | The AM335x SPI NOR barebox update handlers only writes a file to a device, so use the generic handler for this purpose. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: am33xx: Add support for reset reason detectionWadim Egorov2015-03-021-0/+1
| | | | | | | Also activate in defconfig. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sizes.h: move include/sizes.h to include/linux/sizes.hMasahiro Yamada2015-01-085-5/+5
| | | | | | | | | | | | | | This file originates in Linux. Linux has it under include/linux/ directory since commit dccd2304cc90. Let's move it to the same place as well in barebox. This commit was generated by the following commands: find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:' git mv include/sizes.h include/linux/ Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: am335x: Add register of boot devicesTeresa Gámez2014-11-031-0/+1
| | | | | | | | | | Add support for registering disabled boot devices from oftree. Creating a device tree with all bootable devices disabled, makes it possible to only enable and register the devices needed to load the next stage bootloader. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: am33xx: Add rmii2_crs_dv mux selection in SMA2 registerWadim Egorov2014-11-031-0/+1
| | | | | | | | | | | | | "Silicon revision 1.0 devices only provide the MMC2_DAT7 signal when Mode3 is selected. Silicon revision 2.0 and newer devices implement another level of pin multiplexing which provides the original MMC2_DAT7 signal or RMII2_CRS_DV signal when Mode3 is selected. This new level of of pin multiplexing is selected with bit zero of the SMA2 register." See AM335x Sitara Processors Manual. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/musb'Sascha Hauer2014-10-022-0/+3
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| * ARM: AM33xx: Enable USB and USB phy clocksRolf Evers-Fischer2014-09-262-0/+3
| | | | | | | | | | | | | | | | These are necessary for USB support. To make sure they are actually enabled when a USB capable barebox is started call the clock enable function during startup also for the full barebox, not only the MLO. Signed-off-by: Rolf Evers-Fischer <rolf.evers.fischer@delphi.com>
* | ARM: am335x: Add a NAND update handler for the regular bareboxSascha Hauer2014-09-301-1/+7
| | | | | | | | | | | | | | | | | | | | To be able to not only update the MLO in NAND but also the regular barebox image. Since this is implemented with help of the corresponding xload handler this also removes the 'xload' from the Kconfig options and the filename. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: AM33xx: Add AFI GF board supportSascha Hauer2014-09-262-2/+3
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: AM33xx: Add SDRAM size detectionSascha Hauer2014-08-011-0/+2
| | | | | | | | This adds a function which reads back the SDRAM controller settings. This is used in a AM33xx specific barebox entry function and a SDRAM driver which registers a SDRAM memory bank. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: remove address of the Free Software FoundationAntony Pavlov2014-06-111-4/+0
| | | | | | | | | | | | | | | | | | The FSF address has changed; The FSF site says that address is Free Software Foundation 51 Franklin Street, Fifth Floor Boston, MA 02110-1301 USA (see http://www.fsf.org/about/contact/) Instead of updating it each time the address changes, just drop it completely treewide. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: omap: barebox update nand xloadslots handlerWadim Egorov2014-05-191-0/+13
| | | | | | | | - Added barebox nand xloadslots update handler - This handler updates all given xload slots in nand Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: AM33xx: Add SPI bbu handlerSascha Hauer2014-05-151-0/+6
| | | | | | | We already have an update handler for the MLO on SPI, add a update handler for the regular barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: am33xx: Add missing includeSascha Hauer2014-05-151-0/+1
| | | | | | am33xx-generic.h needs memcpy, so include string.h Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: am33xx: Pass uart_base to soft_reset functionSascha Hauer2014-05-151-1/+1
| | | | | | | To make am33xx_uart0_soft_reset more flexible rename it to am33xx_uart_soft_reset and pass the UART base to it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: AM33xx: make bbu handler static inlineSascha Hauer2014-05-151-1/+1
| | | | | | | The static inline wrapper for am33xx_bbu_spi_nor_mlo_register_handler lacked the 'static inline'. add it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: omap3: Add missing includeSascha Hauer2014-02-031-0/+1
| | | | | | omap3-generic.h needs memcpy, include linux/string.h for this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: OMAP: Safe boot info in fixed SRAM addressSascha Hauer2013-12-107-7/+7
| | | | | | | | | | | | | Storing the boot information in the image itself and passing a pointer around between images is cumbersome and doesn't fit well with multiimage support where the pointer we pass around is already occupied by the devicetree. Do the same as U-Boot does and store the boot information at the bottom of the SRAM public stack. To maintain the compatibility between new xloaders and older barebox binaries we still pass the boot information to the next stage via pointer. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/omap-drivers'Sascha Hauer2013-12-062-1/+4
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| * bus: Add omap gpmc driverSascha Hauer2013-11-271-0/+3
| | | | | | | | | | | | | | This adds a devicetree-only driver for to configure the gpmc and its child devices from dt. Currently only NAND is supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * spi: omap: encode register offset into device_idSascha Hauer2013-11-221-1/+1
| | | | | | | | | | | | | | | | | | | | The omap3 and omap4/am33xx spi cores differ in the offset of the registers in the address space. Instead of encoding this into the resources use the platform_device_id mechanism. This is done in preparation for devicetree probe support where the address space is in the devicetree and can't be adjusted. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: OMAP: centralize omap startupSascha Hauer2013-11-223-0/+9
| | | | | | | | | | | | | | | | | | This introduces a single omap_init function which detects the SoC and does all further SoC initialization. This is done to get rid of initcalls without proper SoC protection. The same has been done for i.MX already. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: OMAP: Make debug_ll UART Kconfig selectableSascha Hauer2013-11-221-36/+35
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: am33xx: Add am33xx_ prefix to SoC specific functionsSascha Hauer2013-11-221-2/+2
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: OMAP: Make cpu_is_* macros runtime if necessarySascha Hauer2013-11-221-11/+29
| | | | | | | | | | | | | | Currently unused, just preparation for the next steps when we'll get multiarch support for OMAP. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: OMAP: select correct reset_cpu function at runtimeSascha Hauer2013-11-223-0/+6
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: OMAP: Add SoC prefix to running_in_* functionsSascha Hauer2013-11-223-4/+9
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* i2c-omap: Update driverJan Weitzel2013-09-271-4/+5
| | | | | | | | | | | | | The driver didn't work well with at24 driver. NACKS are lost. Errors are lost in isr due to the local variable err. Also we didn't wait for bus free in omap_i2c_xfer_msg. Fix issues and get other improvements from linux kernel Tested on OMAP4 and AM335x Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: OMAP: register OMAP specific barebox bootm handlerSascha Hauer2013-09-271-0/+1
| | | | | | | | | The OMAP ROM code passes the boot information via r0 to the bootloader. Add an OMAP specific barebox handler to pass this information to the next stage. This allows us to chainload bootloaders without loosing the information where we booted from. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/omap'Sascha Hauer2013-09-0511-15/+155
|\ | | | | | | | | Conflicts: arch/arm/boards/pcm051/env/config
| * PCM051: Fixup DDRPLLTeresa Gámez2013-09-051-0/+1
| | | | | | | | | | | | | | The correct DDRPLL for PCM051 is 303MHz. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: am33xx: make DDR PLL frequency configurableSascha Hauer2013-08-271-2/+4
| | | | | | | | | | | | Needed for 400MHz DDR3. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: am33xx: Add mmc1 registration helperSascha Hauer2013-08-271-0/+6
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: am33xx: implement cpu revision decodingJan Luebbe2013-08-273-2/+11
| | | | | | | | | | Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: am33xx: Cleanup of lowlevel codeTeresa Gámez2013-08-271-0/+44
| | | | | | | | | | | | | | | | | | There is a lot of duplicate lowlevel code between the am33xx boards. Move this code to am33xx_generic and create structs for sdram settings. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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