| Commit message (Collapse) | Author | Age | Files | Lines |
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Currently arch specific headers can be included with
longer possible as there won't be a single mach anymore.
Move all socfpga specific header files to include/mach/socfpga/ to
prepare for multi-arch support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fix the following warnings
arch/arm/mach-socfpga/arria10-reset-manager.c:152:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q1' [-Wmissing-prototypes]
152 | void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm/mach-socfpga/arria10-reset-manager.c:226:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q2' [-Wmissing-prototypes]
226 | void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm/mach-socfpga/arria10-reset-manager.c:272:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q3' [-Wmissing-prototypes]
272 | void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm/mach-socfpga/arria10-reset-manager.c:329:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q4' [-Wmissing-prototypes]
329 | void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that
is already supported in barebox.
Both a the same in some parts, but totaly different in
others. Most of the hardware blocks are the same in the
SoC parts. The OCRAM is larger on the Arria10 and the
SDRAM controller is different.
The serial core only supports 32bit accesses (different to
the 8bit accesses on the Cyclone5).
As Arria10 has 256KB of OCRAM, it is possible to fit a larger
barebox (and/or use PBL) instead of the two stage bootprocess
used on the Cyclone5 and its 64KB OCRAM.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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