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* ARM: socfpga: Arria10: support programming FPGA in PBLSteffen Trumtrar2018-08-081-2/+0
| | | | | | | | | | | | | | | | | | | | Some Arria10 boards don't have the FPGA programmed externally. Instead barebox needs to do that. As the Arria10 has the SDRAM controller in the FPGA, the first thing we need to do is, configure the FPGA before the SDRAM can even be used. It works like this: 1. boot ROM fetches the PBL from MMC 2. read the MBR from MMC (this depends on the setup done by the boot ROM) 3. read the Bitstream from the MMC and program the FPGA 4. re-read the barebox image from MMC, this time with the full barebox that is appended to the PBL 5. jump into the full barebox Only supported boot device is eMMC. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add arria10 supportSteffen Trumtrar2017-05-031-0/+12
| | | | | | | | | | | | | | | | | | Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: make debug_ll configurableSteffen Trumtrar2017-05-031-25/+44
| | | | | | | | Allow configuring the serial port and clock rate instead of hardcoding it. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Add Altera SoCFPGA supportSascha Hauer2013-09-231-0/+55
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>