barebox - barebox master repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	ARM: socfpga: mach/pll_config.h: add guard macro	Antony Pavlov	2018-04-12	1	-0/+4
\| \| \| \| \|	Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: socfpga: rename socfpga->cyclone5	Steffen Trumtrar	2017-05-03	1	-1/+1
\| \| \| \| \| \| \| \|	Prepare the SoCFPGA code base for different system types (Arria10, Stratix10,...). Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: socfpga: clkmgr: set alteragrp clocks	Steffen Trumtrar	2015-01-13	1	-0/+3
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Altera's U-Boot tree has following commit FogBugz #159721: Enhance Arria V MPU clock to 1050MHz It writes to the two undocumented registers CLKMGR_ALTERAGRP_MPUCLK and CLKMGR_ALTERAGRP_MAINCLK to setup the SoC for higher clocks. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: Add Altera SoCFPGA support	Sascha Hauer	2013-09-23	1	-0/+53
	Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>