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* ARM: socfpga: cyclone5-system-manager.h: remove definesSteffen Trumtrar2019-10-181-11/+0
| | | | | | | | These defines are common for arria10 and cyclone5. Instead of having them here, they are moved to drivers/net/designware_socfpga.c. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10-xload: fix Wmissing-prototypesSteffen Trumtrar2019-10-181-0/+1
| | | | | | | | | | | | Fix the warning: arch/arm/mach-socfpga/arria10-xload.c:17:5: warning: no previous prototype for 'a10_update_bits' [-Wmissing-prototypes] 17 | int a10_update_bits(unsigned int reg, unsigned int mask, | ^~~~~~~~~~~~~~~ Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: clock-manager: fix Wmissing-prototypesSteffen Trumtrar2019-10-181-0/+1
| | | | | | | | | | | | Fix the warning arch/arm/mach-socfpga/arria10-clock-manager.c:113:14: warning: no previous prototype for 'arria10_cm_get_mmc_controller_clk_hz' [-Wmissing-prototypes] 113 | unsigned int arria10_cm_get_mmc_controller_clk_hz(void) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: reset-manager: fix Wmissing-prototypesSteffen Trumtrar2019-10-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following warnings arch/arm/mach-socfpga/arria10-reset-manager.c:152:6: warning: no previous prototype for 'arria10_reset_deassert_shared_peripherals_q1' [-Wmissing-prototypes] 152 | void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm/mach-socfpga/arria10-reset-manager.c:226:6: warning: no previous prototype for 'arria10_reset_deassert_shared_peripherals_q2' [-Wmissing-prototypes] 226 | void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm/mach-socfpga/arria10-reset-manager.c:272:6: warning: no previous prototype for 'arria10_reset_deassert_shared_peripherals_q3' [-Wmissing-prototypes] 272 | void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm/mach-socfpga/arria10-reset-manager.c:329:6: warning: no previous prototype for 'arria10_reset_deassert_shared_peripherals_q4' [-Wmissing-prototypes] 329 | void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Cleanup stack offset cargo cultSascha Hauer2019-09-091-1/+1
| | | | | | | | | Most callers of arm_setup_stack substract a fixed offset of 8, 12 or 16 bytes from the stack top. This is unnecessary as on ARM we have a stack that decrements before storing values. Substracting this offset probably goes back to the U-Boot version we forked from. Stop this now. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: generate smaller images when multiple boards are selectedSascha Hauer2018-11-192-63/+63
| | | | | | | | | | | | | | | The socfpga xload images are limited to 64KiB. This doesn't fit if multiple boards are selected. The reason is that we include huge C files and arrays in the early init code which get compiled once for each board. -ffunction-sections is without effect here since all functions have the same name and hence we get the same function multiple times in the same section. To overcome this we surround all function names with a SECT() macro which is used to add a board specific prefix to the section names. This way -ffunction-sections can now do its work and discard unused functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add lowlevel header with common codeSteffen Trumtrar2018-11-061-0/+80
| | | | | | | | | | Apart from the RAM size, all cyclone5-based Socfpga boards use the same lowlevel code. Instead of duplicating it for every board, move it to mach-socfpga and provide a macro to use it in the boardspecific code. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2018-10-091-5/+5
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| * ARM: socfpga: Add missing inline to noop functionsSascha Hauer2018-10-031-5/+5
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: socfpga: Arria10: add missing staticSascha Hauer2018-10-081-1/+1
|/ | | | | | Avoid "multiple definition of `a10_wait_for_usermode'" Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: Arria10: support programming FPGA in PBLSteffen Trumtrar2018-08-085-2/+137
| | | | | | | | | | | | | | | | | | | | Some Arria10 boards don't have the FPGA programmed externally. Instead barebox needs to do that. As the Arria10 has the SDRAM controller in the FPGA, the first thing we need to do is, configure the FPGA before the SDRAM can even be used. It works like this: 1. boot ROM fetches the PBL from MMC 2. read the MBR from MMC (this depends on the setup done by the boot ROM) 3. read the Bitstream from the MMC and program the FPGA 4. re-read the barebox image from MMC, this time with the full barebox that is appended to the PBL 5. jump into the full barebox Only supported boot device is eMMC. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10-reset-manager: don't reset bootsourceSteffen Trumtrar2018-08-082-0/+7
| | | | | | | | Arria10 init code resets all peripherals. Convert this to keep the bootmedium out of reset and keep the setup done by the boot ROM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10-init: split pinsetupSteffen Trumtrar2018-08-081-0/+2
| | | | | | | | | Move the setup of the shared- and fpgapins to its own function. These pins can only be configured and let out of reset after the FPGA has been programmed. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add SMP_TWD_ADDR for Arria10Steffen Trumtrar2018-08-081-0/+1
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10: add ocram base addressSteffen Trumtrar2018-08-081-0/+1
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: mach/pll_config.h: add guard macroAntony Pavlov2018-04-121-0/+4
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* net: add SoCFPGA-specific designware driverSteffen Trumtrar2018-01-111-0/+3
| | | | | | | Add a driver for the SoCFPGA-specific version of the designware ethernet ip core. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2017-05-0524-48/+1326
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| * ARM: socfpga: add arria10 supportSteffen Trumtrar2017-05-039-0/+1267
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: make debug_ll configurableSteffen Trumtrar2017-05-031-25/+44
| | | | | | | | | | | | | | | | Allow configuring the serial port and clock rate instead of hardcoding it. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: rename socfpga->cyclone5Steffen Trumtrar2017-05-0315-23/+15
| | | | | | | | | | | | | | | | Prepare the SoCFPGA code base for different system types (Arria10, Stratix10,...). Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: socfpga: change param_type struct nameSascha Hauer2017-04-101-1/+1
|/ | | | | | | | We are going to introduce a "enum param_type" in barebox, so rename the struct type of the same name in the socfpga sequencer code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* whole tree: remove trailing whitespacesDu Huanpeng2016-04-211-219/+219
| | | | | Signed-off-by: Du Huanpeng <u74147@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* socfpga: Allow setting partition xloader boots from for mmcTrent Piepho2015-12-141-0/+4
| | | | | | | | | | | | | | | | The xloader boots the 2nd stage barebox from socfpga_barebox_part when using NOR. But when using MMC it boots from a hardcoded "disk0.1". Add the mmc device name to the partition description and use it for mmc booting. Add an extern declaration of socfpga_barebox_part to the socfpga header so that a board can change it to use a different partition. Initialize socfpga_barebox_part to the default value instead of NULL to avoid the NULL check later. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/spi-nor'Sascha Hauer2015-06-092-0/+7
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| * ARM: socfpga: xload: support qspi bootsourceSteffen Trumtrar2015-05-292-0/+7
| | | | | | | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: socfpga: update sdram calibration to 15.0Steffen Trumtrar2015-05-152-234/+61
|/ | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: cleanup sequencer warningsSteffen Trumtrar2015-01-132-233/+10
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: Import sequencer code from generated ubootMarkus Pargmann2015-01-136-2566/+3929
| | | | | | | | | This patch imports the sequencer code from uboot using the new script scripts/socfpga_get_sequencer. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: clkmgr: bypass debug root clockSteffen Trumtrar2015-01-131-0/+1
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: clkmgr: set alteragrp clocksSteffen Trumtrar2015-01-132-0/+9
| | | | | | | | | | | | | | | | Altera's U-Boot tree has following commit FogBugz #159721: Enhance Arria V MPU clock to 1050MHz It writes to the two undocumented registers CLKMGR_ALTERAGRP_MPUCLK and CLKMGR_ALTERAGRP_MAINCLK to setup the SoC for higher clocks. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: avoid using external regulator for PLLSteffen Trumtrar2015-01-131-0/+5
| | | | | | | | From Altera U-Boot: FogBugz #210587: Fixing PLL HW configuration issue Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: update sdram calibration to 14.0Steffen Trumtrar2014-12-082-91/+159
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: move iocsr from mach to board folderSteffen Trumtrar2014-12-082-9/+11
| | | | | | | | | | The current iocsr-config-cyclone5.c is actually board specific, although the file name suggests otherwise. As the file was generated for the SoCkit, move it there and add a new one for the socrates. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Firmware: socfpga: Add SoCFPGA FPGA program supportSascha Hauer2014-09-091-0/+2
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfgpa: Remove redundant assignmentAlexander Shiyan2014-02-171-1/+0
| | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfgpa: update sequencerSteffen Trumtrar2013-12-041-18/+41
| | | | | | | | Quartus II v13.1 generates updated sequencer.[ch] files. Integrate the changes into the current driver. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Add Altera SoCFPGA supportSascha Hauer2013-09-2314-0/+6073
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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