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Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that
is already supported in barebox.
Both a the same in some parts, but totaly different in
others. Most of the hardware blocks are the same in the
SoC parts. The OCRAM is larger on the Arria10 and the
SDRAM controller is different.
The serial core only supports 32bit accesses (different to
the 8bit accesses on the Cyclone5).
As Arria10 has 256KB of OCRAM, it is possible to fit a larger
barebox (and/or use PBL) instead of the two stage bootprocess
used on the Cyclone5 and its 64KB OCRAM.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Prepare the SoCFPGA code base for different system types
(Arria10, Stratix10,...).
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fixes:
arch/arm/mach-socfpga/xload.c:121:13: warning: assignment discards 'const' qualifier from pointer target type
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fixes:
arm/mach-socfpga/xload.c:31:52: warning: initialization from incompatible pointer type
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The xloader boots the 2nd stage barebox from socfpga_barebox_part when
using NOR. But when using MMC it boots from a hardcoded "disk0.1".
Add the mmc device name to the partition description and use it for
mmc booting.
Add an extern declaration of socfpga_barebox_part to the socfpga
header so that a board can change it to use a different partition.
Initialize socfpga_barebox_part to the default value instead of NULL to
avoid the NULL check later.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since there is no OF support in the xloader on socfpga it uses the
platform_data system. There needs to be a way to supply the
equivalent of the DT property bus-width this way to support devices
that need to use a smaller bus.
So that we don't need to put every flag that might get added to the
MMC_CAP list into platform_data, just put the bus width ones into
platform_data.
The socfpga dts sources specify a bus-width of 4 so use that in the
platform_data for socfpga.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This file originates in Linux. Linux has it under include/linux/
directory since commit dccd2304cc90.
Let's move it to the same place as well in barebox.
This commit was generated by the following commands:
find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:'
git mv include/sizes.h include/linux/
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The current implementation fakes a memory-mapped I/O device
at 0x3f8 and 0x2f8, then uses platform read/write functions
to do the actual reading and writing. These platform functions
only exist for the x86 platform; better to move the I/O
routines into the driver and have the driver request I/O ports
using request_ioport_region.
Signed-off-by: Michel Stam <michel@reverze.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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