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* ARM: socfpga: cyclone5-system-manager.h: remove definesSteffen Trumtrar2019-10-181-11/+0
| | | | | | | | These defines are common for arria10 and cyclone5. Instead of having them here, they are moved to drivers/net/designware_socfpga.c. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10-xload: fix Wmissing-prototypesSteffen Trumtrar2019-10-181-0/+1
| | | | | | | | | | | | Fix the warning: arch/arm/mach-socfpga/arria10-xload.c:17:5: warning: no previous prototype for 'a10_update_bits' [-Wmissing-prototypes] 17 | int a10_update_bits(unsigned int reg, unsigned int mask, | ^~~~~~~~~~~~~~~ Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: clock-manager: fix Wmissing-prototypesSteffen Trumtrar2019-10-181-0/+1
| | | | | | | | | | | | Fix the warning arch/arm/mach-socfpga/arria10-clock-manager.c:113:14: warning: no previous prototype for 'arria10_cm_get_mmc_controller_clk_hz' [-Wmissing-prototypes] 113 | unsigned int arria10_cm_get_mmc_controller_clk_hz(void) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: reset-manager: fix Wmissing-prototypesSteffen Trumtrar2019-10-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following warnings arch/arm/mach-socfpga/arria10-reset-manager.c:152:6: warning: no previous prototype for 'arria10_reset_deassert_shared_peripherals_q1' [-Wmissing-prototypes] 152 | void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm/mach-socfpga/arria10-reset-manager.c:226:6: warning: no previous prototype for 'arria10_reset_deassert_shared_peripherals_q2' [-Wmissing-prototypes] 226 | void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm/mach-socfpga/arria10-reset-manager.c:272:6: warning: no previous prototype for 'arria10_reset_deassert_shared_peripherals_q3' [-Wmissing-prototypes] 272 | void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm/mach-socfpga/arria10-reset-manager.c:329:6: warning: no previous prototype for 'arria10_reset_deassert_shared_peripherals_q4' [-Wmissing-prototypes] 329 | void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2019-09-121-51/+12
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| * ARM: socfpga: fix xload on arria10Steffen Trumtrar2019-08-191-51/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Since the commit 5a1a5ed2537d7d12f851f3778707681d6c08d6e8 ARM: images: use piggydata the loading mechanism in the arria10 xload is neither functional nor needed. Now, barebox has/can be loaded like a normal image, so the filesize, that is written to the barebox header, can be evaluated. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Cleanup stack offset cargo cultSascha Hauer2019-09-091-1/+1
|/ | | | | | | | | Most callers of arm_setup_stack substract a fixed offset of 8, 12 or 16 bytes from the stack top. This is unnecessary as on ARM we have a stack that decrements before storing values. Substracting this offset probably goes back to the U-Boot version we forked from. Stop this now. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: Cyclone5: remove watchdog_disable()Ian Abbott2019-04-231-17/+0
| | | | | | | | | watchdog_disable() is left over from the original SoCFPGA commit and nothing calls it. Remove it to avoid a '-Wmissing-prototypes' warning from the compiler. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: generate smaller images when multiple boards are selectedSascha Hauer2018-11-192-63/+63
| | | | | | | | | | | | | | | The socfpga xload images are limited to 64KiB. This doesn't fit if multiple boards are selected. The reason is that we include huge C files and arrays in the early init code which get compiled once for each board. -ffunction-sections is without effect here since all functions have the same name and hence we get the same function multiple times in the same section. To overcome this we surround all function names with a SECT() macro which is used to add a board specific prefix to the section names. This way -ffunction-sections can now do its work and discard unused functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: select GPIOLIB for non-xloadSteffen Trumtrar2018-11-191-0/+1
| | | | | | | | SoCFPGA has GPIOs. Select it for the normal bootloader. For the xload barebox, do not select it to not waste space. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add lowlevel header with common codeSteffen Trumtrar2018-11-061-0/+80
| | | | | | | | | | Apart from the RAM size, all cyclone5-based Socfpga boards use the same lowlevel code. Instead of duplicating it for every board, move it to mach-socfpga and provide a macro to use it in the boardspecific code. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2018-10-091-5/+5
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| * ARM: socfpga: Add missing inline to noop functionsSascha Hauer2018-10-031-5/+5
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: socfpga: Arria10: Fix compiler warningSascha Hauer2018-10-081-1/+1
| | | | | | | | | | | | | | | | | | Fixes: arch/arm/mach-socfpga/arria10-xload.c: In function 'arria10_prepare_mmc': arch/arm/mach-socfpga/arria10-xload.c:339:40: warning: dereferencing 'void *' pointer Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: socfpga: Arria10: add missing staticSascha Hauer2018-10-081-1/+1
|/ | | | | | Avoid "multiple definition of `a10_wait_for_usermode'" Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: Arria10: support programming FPGA in PBLSteffen Trumtrar2018-08-089-5/+833
| | | | | | | | | | | | | | | | | | | | Some Arria10 boards don't have the FPGA programmed externally. Instead barebox needs to do that. As the Arria10 has the SDRAM controller in the FPGA, the first thing we need to do is, configure the FPGA before the SDRAM can even be used. It works like this: 1. boot ROM fetches the PBL from MMC 2. read the MBR from MMC (this depends on the setup done by the boot ROM) 3. read the Bitstream from the MMC and program the FPGA 4. re-read the barebox image from MMC, this time with the full barebox that is appended to the PBL 5. jump into the full barebox Only supported boot device is eMMC. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10-reset-manager: don't reset bootsourceSteffen Trumtrar2018-08-084-13/+43
| | | | | | | | Arria10 init code resets all peripherals. Convert this to keep the bootmedium out of reset and keep the setup done by the boot ROM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10: fix SDMMC phase shiftSteffen Trumtrar2018-08-081-1/+1
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10: set default TEXTBASESteffen Trumtrar2018-08-081-0/+1
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10-init: split pinsetupSteffen Trumtrar2018-08-082-23/+28
| | | | | | | | | Move the setup of the shared- and fpgapins to its own function. These pins can only be configured and let out of reset after the FPGA has been programmed. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add SMP_TWD_ADDR for Arria10Steffen Trumtrar2018-08-081-0/+1
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10: add ocram base addressSteffen Trumtrar2018-08-081-0/+1
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: arria10: move debug_ll to common codeSteffen Trumtrar2018-08-082-0/+4
| | | | | | | | Instead of copy+pasting the debug_ll messages to every new board, move them to the respective functions. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: arria10: enable errata 794072 and 845369Oleksij Rempel2018-07-021-0/+4
| | | | | | | | Enable workarounds for two of the errata the CPU is affected with. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: mach/pll_config.h: add guard macroAntony Pavlov2018-04-121-0/+4
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: remove nonexistent Kconfig dependencySascha Hauer2018-04-061-5/+0
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: SoCFPGA: remove emac init codeSteffen Trumtrar2018-01-111-35/+0
| | | | | | | | There is a proper driver now that handles the PHY setup for SoCFPGA. Get rid of the code from mach-socfpga. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* net: add SoCFPGA-specific designware driverSteffen Trumtrar2018-01-111-0/+3
| | | | | | | Add a driver for the SoCFPGA-specific version of the designware ethernet ip core. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: remove unused fpgaintf setupSteffen Trumtrar2017-06-301-8/+0
| | | | | | | | | | | The disable bits for the ethernet interfaces between FPGA and HPS are read and configured, but never written back. The configuration itself doesn't make that much sense however. So instead of writing it back to the register, remove the whole read-modify operation altogether. Reported-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: fix QSPI platform data initLucas Stach2017-05-171-1/+1
| | | | | | | | The struct member has been renamed, fix it. Fixes: fddf254b8b9a (mtd: spi-nor: cadence: change devicetree bindings to upstream) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2017-05-0543-269/+3719
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| * ARM: socfpga: add support for reflex achilles boardSteffen Trumtrar2017-05-041-0/+5
| | | | | | | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: add arria10 supportSteffen Trumtrar2017-05-0320-196/+3420
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: make debug_ll configurableSteffen Trumtrar2017-05-031-25/+44
| | | | | | | | | | | | | | | | Allow configuring the serial port and clock rate instead of hardcoding it. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: rename socfpga->cyclone5Steffen Trumtrar2017-05-0326-49/+251
| | | | | | | | | | | | | | | | Prepare the SoCFPGA code base for different system types (Arria10, Stratix10,...). Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/parameter-types'Sascha Hauer2017-05-051-1/+1
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| * | ARM: socfpga: change param_type struct nameSascha Hauer2017-04-101-1/+1
| |/ | | | | | | | | | | | | | | We are going to introduce a "enum param_type" in barebox, so rename the struct type of the same name in the socfpga sequencer code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / mtd: spi-nor: cadence: change devicetree bindings to upstreamSteffen Trumtrar2017-04-191-1/+1
|/ | | | | | | | | Upstream devicetree bindings where changed to use "cdns,is-decoded-cs" instead of "external-decoder". Use it. Also, get rid of the clock-names "qspi_clk" dependency. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: remove unused entry from MakefileSteffen Trumtrar2017-01-101-1/+0
| | | | | | | | There is no fpga.c file. Remove the entry. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: fix compiler warningSascha Hauer2017-01-101-1/+1
| | | | | | | Fixes: arch/arm/mach-socfpga/xload.c:121:13: warning: assignment discards 'const' qualifier from pointer target type Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: fix compiler warningSascha Hauer2017-01-101-1/+1
| | | | | | | Fixes: arm/mach-socfpga/xload.c:31:52: warning: initialization from incompatible pointer type Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/defenv'Sascha Hauer2016-10-101-4/+0
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| * Make generic default environment type a use choiceSascha Hauer2016-10-101-4/+0
| | | | | | | | | | | | | | | | So far it was hardcoded for each board if defenv-1 or defenv-2 is used. Make this a user choice so that a particular board no longer enforces a defenv type. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: socfpga: xload: support more qspi partitionsUlrich Ölmann2016-08-181-15/+41
|/ | | | | | Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2016-05-091-219/+219
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| * whole tree: remove trailing whitespacesDu Huanpeng2016-04-211-219/+219
| | | | | | | | | | Signed-off-by: Du Huanpeng <u74147@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | include: Move ns16550 serial platform_data to include/platform_dataSascha Hauer2016-04-151-1/+1
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | include: Move designware eth platform_data to include/platform_dataSascha Hauer2016-04-151-1/+0
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Terasic DE0-Nano-SoC: add supportTim Sander2016-03-011-0/+4
| | | | | | | | | | | | v7: eof whitespace fixes A Patch for supporting the Terasic DE0 NANO-SoC with barebox. The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign Signed-off-by: Tim Sander <tim@krieglstein.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2016-01-112-5/+7
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