| Commit message (Collapse) | Author | Age | Files | Lines |
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To work around an erratum, the previous booting stage may have increased the
amount of rows to fake having 4G of RAM. In that case, we assume the previous
booting stage will have fixed up a proper memory size into the device tree and
don't use the calculated dram size. The erratum itself appears to be
undocumented by Altera/Intel and the workaround was introduced in the Alteras
fork of U-Boot back in 2014 and ported to mainline later, the linked FogBugz
issue is unfortunately not accessible.
[1] github.com/altera-opensource/u-boot-socfpga/commit/93815696dce132ff8abc4ab2f4c195339ff821a0
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Link: https://lore.barebox.org/20231214-fix-socfpga-dram-errata-workaround-v1-1-abfab95e7f69@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Intel documentation states that the FPGA configuration might fail.
This has been observed on the Enclustra AA1+ board where up to 4 retries
where required to configure the FPGA.
Debugging session showed that the data where correctly read from the
eMMC but yet the configuration failed.
This commit introduces a retry loop on the FPGA configuration.
Up to 10 retries (arbitrary) are attempted.
As the hardware can't be used anyway without the FPGA loaded, this
doesn't introduce any boot time problems. Taking longer is better than
just hang()ing.
Signed-off-by: Bruno Knittel <bruno.knittel@bruker.com>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Link: https://lore.barebox.org/20231115-arria10-fpga-reload-on-failure-v2-1-6a45f125c9c2@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Currently arch specific headers can be included with
longer possible as there won't be a single mach anymore.
Move all socfpga specific header files to include/mach/socfpga/ to
prepare for multi-arch support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The '_d' suffix was originally introduced in case we want to import
Linux struct device as a separate struct into barebox. Over time it
became clear that this won't happen, instead barebox struct device_d
is basically the same as Linux struct device. Rename the struct name
accordingly to make porting Linux code easier.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20221214123512.189688-3-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When DDR firewall configuration is updated the F2SDRAM bridges need to
be brought from reset.
Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>
Link: https://lore.barebox.org/20221101103327.985435-2-uvv.mail@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Incorrect enable bits were used in initialization sequence of SDRAM
firewall. This enables the FPGA to access regions of SDRAM, which were
previously inaccessible.
Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>
Link: https://lore.barebox.org/20221101103327.985435-1-uvv.mail@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Setting BIT(1) in the ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE results in
mapping the OCRAM to 0x0, at least for the CPU. Peripherals doing
DMA like the SDMMC controller see the SDRAM instead. Linux happens
to use this low memory for DMA sometimes and things explode nicely
at that point.
Clear the OCRAM mapping so that both the CPU and DMA controllers access
SDRAM.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20221026125451.3357318-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Cortex A9 on the Arria10 has multiple known errata.
Enable at least the currently supported ones in barebox.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Link: https://lore.barebox.org/20220826064956.507125-2-s.trumtrar@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Link: https://lore.barebox.org/20220801120708.2511165-7-s.trumtrar@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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To optimize the image size, use compressed devicetrees.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Link: https://lore.barebox.org/20220801120708.2511165-3-s.trumtrar@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Patterns like [ "$bootsource" = mmc ] && boot mmc$bootsource_instance
expect that ${bootsource_instance} and MMC aliases align, which may not
always be the case. In preparation for adding a new bootsource_set
function that consults an optional mapping table from bootrom
bootsource_instance to board-specific device numbering, rename all
existing instances to bootsource_set_raw. While at it, clean up the
legacy split into bootsource_set and bootsource_set_instance and have
the new bootsource_set_raw accept both arguments at once.
No functional change intended.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220720055042.3510276-2-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Record GPL-2.0-only as license for all files lacking an explicit license
statement.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220103120539.1730644-11-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Record GPL-2.0-only as license for all files lacking an explicit license
statement.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220103120539.1730644-9-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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To verify only Kconfig/Makefile is touched:
git show --numstat --format=oneline HEAD | grep -v 'Kconfig\|Makefile'
will print only arch/powerpc/Kbuild.
To verify nothing unexpected is added:
git show -U0 | grep '^-[^-]\|^+[^+]' | sort -u
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220103120539.1730644-3-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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To make changes to the SDRAM controller effective, the APPLYCFG bit must
be set after programming the bitstream to the FPGA. This has to be done
without any SDRAM usage. Therefore copy the function to execute to the
OCRAM and execute it from there.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Link: https://lore.barebox.org/20210625085944.11260-1-s.trumtrar@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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A timeout is never detected as timeout is tested for being smaller than
0 which never happens for an unsigned variable. Change to a signed type.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210517185424.32145-3-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Terasic DE10-Nano board is based on CycloneV SoCFPGA (5CSEBA6) with
What has been tested to work:
- SD card
- Gigabit network
- FPGA (FPPx16 & FPPx32)
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Link: https://lore.barebox.org/20210531194019.951-1-gwenj@trabucayre.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Do not hand over control to a second stage barebox if its embedded CRC checksum
is invalid.
Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
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The size of the buffer allocated in the function is needed if it shall be
inspected more closely later. Therefore optionally return it via a new pointer
argument.
Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
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The size of the buffer allocated in the function is needed if it shall be
inspected more closely later. Therefore optionally return it via a new pointer
argument.
Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
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With incoming changes to choose a specific reset method, give all
currently unnamed "default" reset handlers a name:
- soc reset via SoC-specific means
- soc-wdt reset via SoC watchdog timer
- vector reset via jump to reset vector
- efi reset via EFI firmware
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This reverts commit a83c97f2a4065ef7209f123b837fa5103f984c6a.
The dead code elimination with thin archive can cope with the same
symbol names. Revert the workaround.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We already have one ARCH_TEXT_BASE in the file, which sets a value of
zero. MACH_SOCFPGA_CYCLONE5 and MACH_SOCFPGA_ARRIA10 aren't defined
anywhere and are listed in no defconfigs, thus drop the duplicate
option.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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These defines are common for arria10 and cyclone5.
Instead of having them here, they are moved to drivers/net/designware_socfpga.c.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fix the warning:
arch/arm/mach-socfpga/arria10-xload.c:17:5: warning: no previous prototype for
'a10_update_bits' [-Wmissing-prototypes]
17 | int a10_update_bits(unsigned int reg, unsigned int mask,
| ^~~~~~~~~~~~~~~
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fix the warning
arch/arm/mach-socfpga/arria10-clock-manager.c:113:14: warning: no previous prototype for
'arria10_cm_get_mmc_controller_clk_hz' [-Wmissing-prototypes]
113 | unsigned int arria10_cm_get_mmc_controller_clk_hz(void)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fix the following warnings
arch/arm/mach-socfpga/arria10-reset-manager.c:152:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q1' [-Wmissing-prototypes]
152 | void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm/mach-socfpga/arria10-reset-manager.c:226:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q2' [-Wmissing-prototypes]
226 | void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm/mach-socfpga/arria10-reset-manager.c:272:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q3' [-Wmissing-prototypes]
272 | void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm/mach-socfpga/arria10-reset-manager.c:329:6: warning: no previous prototype for
'arria10_reset_deassert_shared_peripherals_q4' [-Wmissing-prototypes]
329 | void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since the commit
5a1a5ed2537d7d12f851f3778707681d6c08d6e8
ARM: images: use piggydata
the loading mechanism in the arria10 xload is neither functional nor needed.
Now, barebox has/can be loaded like a normal image, so the filesize, that is
written to the barebox header, can be evaluated.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Most callers of arm_setup_stack substract a fixed offset of 8, 12 or 16
bytes from the stack top. This is unnecessary as on ARM we have a stack
that decrements before storing values. Substracting this offset probably
goes back to the U-Boot version we forked from. Stop this now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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watchdog_disable() is left over from the original SoCFPGA commit and
nothing calls it. Remove it to avoid a '-Wmissing-prototypes' warning
from the compiler.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The socfpga xload images are limited to 64KiB. This doesn't fit if
multiple boards are selected. The reason is that we include huge
C files and arrays in the early init code which get compiled once
for each board. -ffunction-sections is without effect here since all
functions have the same name and hence we get the same function
multiple times in the same section.
To overcome this we surround all function names with a SECT() macro which
is used to add a board specific prefix to the section names. This way
-ffunction-sections can now do its work and discard unused functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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SoCFPGA has GPIOs. Select it for the normal bootloader. For the xload barebox,
do not select it to not waste space.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Apart from the RAM size, all cyclone5-based Socfpga boards use the
same lowlevel code. Instead of duplicating it for every board, move
it to mach-socfpga and provide a macro to use it in the boardspecific
code.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fixes:
arch/arm/mach-socfpga/arria10-xload.c: In function 'arria10_prepare_mmc':
arch/arm/mach-socfpga/arria10-xload.c:339:40: warning: dereferencing 'void *' pointer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Avoid "multiple definition of `a10_wait_for_usermode'"
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Some Arria10 boards don't have the FPGA programmed externally.
Instead barebox needs to do that. As the Arria10 has the SDRAM
controller in the FPGA, the first thing we need to do is,
configure the FPGA before the SDRAM can even be used.
It works like this:
1. boot ROM fetches the PBL from MMC
2. read the MBR from MMC (this depends on the setup done by the boot ROM)
3. read the Bitstream from the MMC and program the FPGA
4. re-read the barebox image from MMC, this time with the full barebox
that is appended to the PBL
5. jump into the full barebox
Only supported boot device is eMMC.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Arria10 init code resets all peripherals. Convert this to keep the bootmedium
out of reset and keep the setup done by the boot ROM.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Move the setup of the shared- and fpgapins to its own function.
These pins can only be configured and let out of reset after the FPGA has been
programmed.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Instead of copy+pasting the debug_ll messages to every new board,
move them to the respective functions.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Enable workarounds for two of the errata the CPU is affected
with.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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