barebox - barebox master repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	firmware-zynqmp: extend driver with fpga relavant functions	Thomas Haemmerle	2019-10-28	1	-1/+13
\| \| \| \| \| \| \| \|	Port functions from xlnx-linux to get FPGA status and invoke bitstream loading. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: zynqmp: move PAYLOAD_ARG_CNT to firmware header	Michael Tretter	2019-03-18	1	-0/+2
\| \| \| \| \| \| \| \|	In order to use the query() call, the users of the firmware driver need to know the number of arguments. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	firmware-zynqmp: port from linux	Thomas Haemmerle	2019-02-27	1	-0/+66
\| \| \| \| \| \| \|	Port Xilinx Zynq MPSoC Firmware layer driver from linux. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: zynqmp: add support for Xilinx ZCU104 board	Michael Tretter	2018-12-10	1	-0/+31
	Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP) and the Xilinx ZCU104 board. Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL) already took care of initializing the RAM. Also for debug_ll, the UART is expected to be already setup correctly. Thus, you have to add the Barebox binary to a boot image as described in "Chapter 11: Boot and Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual". Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>