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* Merge branch 'for-next/imx'Sascha Hauer2017-02-1376-104/+6272
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| * ARM: i.MX7: Add PSCI supportSascha Hauer2017-02-132-0/+90
| | | | | | | | | | | | | | This adds the SoC specific PSCI bits for i.MX7. Based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add PSCI supportSascha Hauer2017-02-1317-6/+1092
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains the barebox implementation for the ARM "Power State Coordination Interface" (PSCI). The interface is aimed at the generalization of code in the following power management scenarios: * Core idle management. * Dynamic addition and removal of cores, and secondary core boot. * big.LITTLE migration. * System shutdown and reset. In practice, all that's currently implemented is a way to enable the secondary core one some SoCs. With PSCI the Kernel is either started in nonsecure or in Hypervisor mode and PSCI is used to apply power to the secondary cores. The start mode is passed in the global.bootm.secure_state variable. This enum can contain "secure" (Kernel is started in secure mode, means no PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available) or "hyp" (Kernel is started in hyp mode, meaning it can support virtualization). We currently only support putting the secure monitor code into SDRAM, which means we always steal some amount of memory from the Kernel. To keep things simple for now we simply keep the whole barebox binary in memory The PSCI support has been tested on i.MX7 only so far. The only supported operations are CPU_ON and CPU_OFF. The PSCI and secure monitor code is based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add smc call supportSascha Hauer2017-02-083-0/+170
| | | | | | | | | | | | Taken from the Kernel: A wrapper to make a smc call from C. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add UNWIND macroSascha Hauer2017-02-081-0/+6
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: vf610: Add support for ZII VF610 Dev FamilyAndrey Smirnov2017-02-0717-0/+2848
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for ZII VF610 Dev based designs such as: - VF610 Dev, revision B - VF610 Dev, revision C - CFU1, revision A - SPU3, revision A - SCU4 AIB, revision C Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: Initialize CSUSascha Hauer2017-02-061-0/+14
| | | | | | | | | | | | | | The CSU needs to be initialized, otherwise we cannot access memory in non secure mode. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: Add imx7s.dtsiSascha Hauer2017-02-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | Needed for compiling the i.MX7 warp board which already includes this file. This file is necessary because the upstream dtsi file currently assigns MX7D_CLK_DUMMY to the gpt1 clock we use, so we won't get a meaningful clock rate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * pinctrl: i.MX7: Fix LPSR sel_imput settingSascha Hauer2017-02-061-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX7 has two pinmux controllers, the regular and the LPSR controller. The LPSR pinmux controller doesn't have any sel_input registers, instead they can be found in the regular pinmux controller. This means whenever we want to apply the the sel_input setting for the LPSR controller, we have to apply them to the regular controller instead. In barebox take the easy way out and just add the difference of the two base addresses to the register offset. The same issue is present in the Kernel aswell, but when the bootloader already configured the pins correctly nobody notices when the Kernel sel_input setup effectively is a no-op. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM i.MX: Add i.MX6SL supportAlexander Kurz2017-02-022-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Most i.MX6SL infrastructure is already covered in barebox by general i.MX6 support. Missing infrastructure provided in separate commits are * SoC type detection * Clock infrastructure Add the missing fsl,imx6sl-mmdc, so it will not be catched by fsl,imx6q-mmdc and the remaining bits and pieces to provide barebox i.MX6SL SoC support. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM i.MX: add SoC type detection for i.MX6SLAlexander Kurz2017-02-013-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX6 series SoC type is determined by barebox by examining the USB_ANALOG_DIGPROG aka IMX6_ANATOP_SI_REV register. This register is located at a common offset for all mx6 SoC - except for i.MX6SL where a different offset is used. This creates a dilemma while distinguishing the mx6sl from non-mx6sl SOC since the SoC type identification register location is type specific itself. Access to undocumented and probably invalid or unpredictable registers should be avoided as possible. For the mx6sl detection an access to the general USB_ANALOG_DIGPROG @0x260 cannot be avoided when running on mx6sl. This register contained the value 0x00014009 for different mx6sl Rev. 1.2 based e-book readers using MCIMX6L7DVN10AB and MCIMX6L8DVN10AB SoC. This implementation assumes the value of MAJOR_UPPER (here 0x01) to be smaller than the smallest non-6sl MAJOR_UPPER (0x61 for mx6s). Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM i.MX: move cpu_type macros in front of cpu_revision codeAlexander Kurz2017-02-011-20/+20
| | | | | | | | | | | | | | Preparational commit to enable the use of cpu_type macros in imx6_cpu_revision() Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: add AIPS base address definesAlexander Kurz2017-01-303-17/+112
| | | | | | | | | | | | | | Import the ARM IP bus base addresses from IMX7DRM 05/2016 AIPS Memory Map Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: Kconfig: ARCH_IMX7 selects COMMON_CLK_OF_PROVIDERAlexander Kurz2017-01-261-0/+2
| | | | | | | | | | | | | | Build of clk-imx7 depends on selection of COMMON_CLK_OF_PROVIDER Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: vf610-twr: remove unused variableSascha Hauer2017-01-201-1/+0
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: initialize architected timerSascha Hauer2017-01-201-0/+35
| | | | | | | | | | | | | | This is the same that U-Boot does. The registers are not documented. Without this the architected timer on the i.MX7 does not work. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX: Add WaRP7 board supportJuergen Borleis2017-01-208-0/+235
| | | | | | | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX: Add i.MX7 base architecture supportJuergen Borleis2017-01-2011-0/+264
| | | | | | | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX: gpt: Add i.MX7 supportJuergen Borleis2017-01-191-0/+3
| | | | | | | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: rdu2: support QP variantLucas Stach2017-01-184-1/+198
| | | | | | | | | | | | | | | | This adds support for the QuadPlus variant of the board as a separate Barebox binary. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: imx: Add support for ZII RDU2 boardAndrey Smirnov2017-01-1812-0/+948
| | | | | | | | | | | | | | | | Add support for RDU2 board from Zodiac Inflight Innovations. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: vf610-twr: Remove MSCM setup codeAndrey Smirnov2017-01-121-5/+0
| | | | | | | | | | | | | | | | | | Recent kernel versions should have appropriate driver code that sets up interrupt rounting correctly, so there's no need for that to be done in the bootloader. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: iomux-vf610: Add missing pad definitionsAndrey Smirnov2017-01-121-0/+4
| | | | | | | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: vf610: Add low-level pin configuration helperAndrey Smirnov2017-01-121-0/+15
| | | | | | | | | | | | | | | | Add low-level pin configuration helper for early boot code, and convert pinctrl driver to use that code as well. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX6: sabresd: Remove magic numbers in setup_uartAndrey Smirnov2017-01-121-6/+3
| | | | | | | | | | | | | | | | Remove magic numbers in setup_uart and replace them with calls to iomuxv3 helper functions. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: iomuxv3: Add low-level pad configuration routineAndrey Smirnov2017-01-121-0/+17
| | | | | | | | | | | | | | | | Add low-level pad configuration routine that can be used by early boot code as well as leveraged by pinmux driver. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: iomuxv3: Add helper macros to deconstruct iomux_v3_cfg_t valuesAndrey Smirnov2017-01-121-0/+8
| | | | | | | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: iomuxv3: Add low-level pad code to headersAndrey Smirnov2017-01-121-0/+28
| | | | | | | | | | | | | | | | | | Add a basic low-level pad configuration function that can be used to implement early boot pin configuration code as well as shared with various iomuxv3 and vf610 drivers. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: vf610: Ramp CPU clock to maximum frequencyAndrey Smirnov2017-01-121-0/+1
| | | | | | | | | | | | | | | | | | | | Mask ROM leaves the CPU running at 264Mhz, so configure the clock tree such that CPU runs at maximum supported frequency. Maximum supported frequncy is determined from speed grading burned into OCOTP fusebox by the vendor. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: Add fusemap for VF610Andrey Smirnov2017-01-123-41/+65
| | | | | | | | | | | | | | | | Add fusemap header for VF610 and move out fuse definitions that are shared with i.MX6 familiy into a sperate file (ocotp-fusemap.h). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: imx6-fusemap: Fix SJC_RESP_LOCK widthAndrey Smirnov2017-01-121-1/+1
| | | | | | | | | | | | | | | | According to the datasheet SJC_RESP_LOCK is one bit wide, adjust the definition correspondingly. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: ocotp: Add imx_ocotp_sense_enable()Andrey Smirnov2017-01-122-0/+8
| | | | | | | | | | | | | | | | Add imx_ocotp_sense_enable() function to allow changing that aspect of OCOTP driver behaviour before calling imx_ocotp_read_field() Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: ocotp: Initialize OCOTP as early as possibleAndrey Smirnov2017-01-121-1/+1
| | | | | | | | | | | | | | | | | | On Vybrid SoC OCOTP module contains speed grading information that is needed to correctly adjust CPU clock to its maxumum rate, so we need to have this information handy as early as possible. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: ocotp: Add provisions for storing multiple MAC addressesAndrey Smirnov2017-01-121-19/+51
| | | | | | | | | | | | | | | | | | | | | | | | i.MX SoC variants like Vybrid have more than one built-in Ethernet interface and as a consequence support storing more than one MAC address in OCOTP module. Add code to create multiple 'mac_addr<n>' parameters as well as 'mac_addr' as an "alias" to 'mac_addr0' for backwards compatibility. Acked-by: Stefan Lengfeld <s.lengfeld@phytec.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: ocotp: Move memory reversing into a subroutineAndrey Smirnov2017-01-121-7/+13
| | | | | | | | | | | | | | | | Move memory reversing, found in imx_ocotp_get_mac and imx_ocotp_set_mac, into a subroutine to avoid code duplication. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | config: Set UART port 2 as debug portWadim Egorov2017-02-101-1/+1
| | | | | | | | | | Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: phycore-rk3288: Use UART2 as debug outputWadim Egorov2017-02-102-7/+6
| | | | | | | | | | | | | | RK3288's UART2 is the default debug uart interface. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: Fix image size calculationSascha Hauer2017-02-086-4/+10
| | | | | | | | | | | | | | | | | | | | In barebox_non_pbl_start() we do not run at the address we are linked at, so we must read linker variables using ld_var(). Since ld_var() current is not available on arm64 we create two zero sized arrays, one at the begin of the image and one at the end. The difference between both is the image size we are looking for. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: start: Fix boarddata allocationSascha Hauer2017-02-061-1/+1
| | | | | | | | | | | | | | | | | | It's essential that we always pass the same size value to arm_mem_barebox_image(), otherwise the result will be inconsistent. Pass arm_barebox_size instead of barebox_image_size as the latter does not contain the max bss segment size. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm: am33xx: Initialize EMIF REG_PR_OLD_COUNTDaniel Schultz2017-01-304-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on a patch from the U-Boot and fixes two errors with the LCDC. Original commit message from Jyri Sarha [1]: "Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock." The register values are generated by testing, because there is no formula to calculate them. Also from Jyri Sarha [1]: "In practice the only rule to find an optimal value is to find as high as possible REG_PR_OLD_COUNT value that does not produce LCDC FIFO underflows under worst case scenario. The worst case happens when the highest pixel clock videomode with maximum bpp is used while memory subsystem is stressed by endless stream of writes hitting the same memory memory bank (can be the same address)." It only contains the BeagleBone Black and the Phytec SoM, because I don't have other boards. [1] https://patchwork.ozlabs.org/patch/704013/ Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm: omap: OMAP_SERIALBOOT needs console supportLucas Stach2017-01-191-0/+1
| | | | | | | | | | | | | | It is quite useless without a console and breaks the build. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Makefile: format fixJuergen Borleis2017-01-191-1/+1
|/ | | | Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
* Merge branch 'for-next/vybrid'Sascha Hauer2017-01-1221-4304/+62
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| * i.MX: ocotp: Add Vybrid supportAndrey Smirnov2017-01-111-0/+16
| | | | | | | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: ocotp: Account for shadow memory gapsAndrey Smirnov2017-01-111-3/+31
| | | | | | | | | | | | | | | | | | | | Shadow memory does not have a true 1:1 mapping to fuse address space. All i.MX6 devices, with exception of i.MX6SL have a 0x100 byte gap between banks 5 and 6 (or addresses 0x2f and 0x30), so we need to account for that when reading data from shadow memory. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: ocotp: Remove unused #defineAndrey Smirnov2017-01-111-1/+0
| | | | | | | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: Kconfig: Enable OCOTP on VybridAndrey Smirnov2017-01-111-1/+1
| | | | | | | | | | | | | | Enable OCOTP driver on Vybrid as well as i.MX6 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * vf610: Give enet_osc explicit "enet_ext" nameAndrey Smirnov2017-01-111-0/+4
| | | | | | | | | | | | | | | | Give enet_osc explicit "enet_ext" name, since without it, Barebox version of clk_set_parent fails when trying to re-parent "enet_sel". Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: Move clk code from 'mach-imx' to 'drivers'Andrey Smirnov2017-01-1117-3872/+10
| | | | | | | | | | | | | | | | | | Move clk code from 'mach-imx' to 'drivers' to keep the code tree structure closer to that of analogous one from Linux kernel and, arguably although subjective, to keep 'mach-imx' less cluttered. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mvebu'Sascha Hauer2017-01-111-0/+1
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