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* ARM: am335x: Use xz compression for MLOSascha Hauer2020-12-111-5/+1
| | | | | | | the binary built with am335x_mlo_defconfig has grown too big over time. Use xz compression to fit the image into initial SRAM. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: esdctl: Add missing compatibleSascha Hauer2020-11-131-0/+3
| | | | | | | The i.MX8mm has "fsl,imx8mm-ddrc" as compatible, add it to the list of matching nodes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: nxp i.MX8MP evk: make locally used data staticSascha Hauer2020-11-131-9/+9
| | | | | | | Make locally used data static so that it doesn't conflict with other data with the same name. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: layerscape: ppa: Fix use after freeSascha Hauer2020-11-111-0/+1
| | | | | | | | | | | | In of_psci_do_fixup() we want to delete the one job-ring device node which is used by the PPA secure firmware. When we have deleted the node we may not continue the for_each_compatible_node_from() loop, because that would derefence the just deleted node. We only want to delete a single node, so we do not need to continue the loop once we've found the node, so we can fix the issue by breaking out of the loop. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mtd-nand'Sascha Hauer2020-11-1022-1/+22
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| * mtd: nand: Update to Linux-5.9Sascha Hauer2020-11-1022-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This updates the barebox NAND layer and parts of the mtd layer to Linux-5.9. This patch is huge, but the barebox NAND layer is so far away from the Linux NAND layer that a step by step update would have taken ages. Unlike Linux barebox has functions to mark a block as good. This feature has been preserved. Also barebox used to make NAND write support optional, this feature is lost during the update for the sake of better compatibility to the Linux NAND layer. This patch has been tested: - GPMI aka nand_mxs on i.MX6 - nand_imx on i.MX25 - nand_omap_gpmc on AM335x - atmel_nand on Atmel sama5d3 - nand_denali on SoCFPGA Currently untested: - nand_orion - nand_mrvl_nfc - nand_s3c24xx The nand_denali driver is tested with the update of that driver to Linux-5.9 following in the next patch. I could only test the drivers with the NAND chips found on my boards, so there's still enough room for regressions, especially given that the NAND drivers themselves are mostly not updated. With the NAND layer being up-to-date with Linux it should hopefully be easy to update drivers to their Linux counterpart as well if necessary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2020-11-1022-285/+66
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| * | arm: imx: Convert mach headers to SPDXUwe Kleine-König2020-11-0219-272/+51
| | | | | | | | | | | | | | | | | | | | | | | | Replace license and copyright boilerplate by SPDX identfiers for files identified as GPL-2.0-only or GPL-2.0-or-later by licensecheck. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | imx: Fix copyright claimUwe Kleine-König2020-11-021-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The file was created by me in commit c0fcf4dde3c9 ("ARM: i.MX7: provide DDR register definitions") and obviously I failed to adapt our copyright template. While at it, convert to SPDX. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: mmu64: allow to disable null pointer trap on zero pageMichael Tretter2020-10-222-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Barebox uses the zero page to trap NULL pointer dereferences. However, if the SDRAM starts at address 0x0, this makes the first page of the SDRAM inaccessible and makes it impossible to load images to offset 0x0 in the SDRAM. Trapping NULL pointer dereferences on such systems is still desirable. Therefore, add a function to disable the traps if accessing the zero page is necessary and to re-enable the traps after the access is done. The zero_page_memcpy function simplifies copying to the SDRAM, because this is the most common required functionality, but memtest also accesses the zero page and does not use memcpy. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2020-11-103-12/+22
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| * | | ddr: imx8m: clean up entry pointsLucas Stach2020-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDRC address in the memory map and the TF-A parameter store address is the same for all i.MX8M* SoCs. The only difference (for now) is in the power up sequence. Add a enum for the DDRC type, so we can take different code paths in imx8m_ddr_init() depending on the SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: dts: imx6qdl: pfla02: Remove eeprom nodeAlexander Shiyan2020-11-021-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The upstream dtsi now has a eeprom node, so no need to duplicate anymore. Let's keep the "page_size" property for a while. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: dts: imx6qdl: pfla02: document motivation for dropping supplyUwe Kleine-König2020-11-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 84cf5cfa9a0e ("ARM: dts: imx6qdl: pfla02: Remove fec phy-supply") the phy-supply was removed. The motivation however was only given in the commit log. Add a comment accompanying the actual statement to remove the property to make this better findable. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: CCMX51: Add new module ID variantAlexander Shiyan2020-10-281-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for Digi ConnectCore module variant 0x15 Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/imd-checksum'Sascha Hauer2020-11-104-6/+27
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| * | | | ARM: socfpga: xload: evaluate integrity of second stage barebox imagesUlrich Ölmann2020-11-051-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not hand over control to a second stage barebox if its embedded CRC checksum is invalid. Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
| * | | | bootstrap_read_disk(): optionally inform the caller of the buffer sizeUlrich Ölmann2020-06-222-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size of the buffer allocated in the function is needed if it shall be inspected more closely later. Therefore optionally return it via a new pointer argument. Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
| * | | | bootstrap_read_devfs(): optionally inform the caller of the buffer sizeUlrich Ölmann2020-06-224-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size of the buffer allocated in the function is needed if it shall be inspected more closely later. Therefore optionally return it via a new pointer argument. Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
* | | | | Merge branch 'for-next/dts'Sascha Hauer2020-11-102-2/+2
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| * | | | | dts: update to v5.10-rc1Sascha Hauer2020-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | | Merge branch 'for-next/at91'Sascha Hauer2020-11-106-252/+209
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| * | | | | ARM: at91: remove at91sam9x5ek_defconfigSascha Hauer2020-10-191-91/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The at91sam9x5ek is now covered by the at91_multi_defconfig. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: at91: remove at91sam9263ek_defconfigSascha Hauer2020-10-191-88/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The at91sam9263ek is now covered by the at91_multi_defconfig. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: at91: define new at91_multi_defconfigAhmad Fatoum2020-10-192-72/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now have 5 boards supporting multi-image, so add a defconfig that covers these five boards: - Microchip KSZ-9477 EVB - Microchip SAMA5D27-SOM1-EK - Groboards Giantboard - Atmel AT91SAM9263-EK - Atmel AT91SAM9x5 Series Evaluation Kit Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: at91sam9x5ek: Update NAND partitioningSascha Hauer2020-10-191-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current NAND partitioning is derived from the kernel dts. A current barebox built with at91sam9x5ek_defconfig no longer fits into the barebox partition. Also a Kernel built with sama5_defconfig no longer fits into the kernel partition. This makes the board quite unusable for modern setups, so take the step and do an incompatible update of the partitioning. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: at91sam9263ek: Update NAND partitioningSascha Hauer2020-10-191-1/+33
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current NAND partitioning is derived from the kernel dts. A current barebox built with at91sam9263ek_defconfig no longer fits into the barebox partition. Also a Kernel built with sama5_defconfig no longer fits into the kernel partition. This makes the board quite unusable for modern setups, so take the step and do an incompatible update of the partitioning. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | ARM: dts: am335x: Fix pinctrl valuesSascha Hauer2020-11-037-396/+396
| |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux 27c90e5e48d0 ("ARM: dts: am33xx-l4: change #pinctrl-cells from 1 to 2") changes #pinctrl-cells from 1 to 2. With this we need three values per pin. the upstream dts files use the AM33XX_PADCONF() macro which handles this change, but the barebox dts files do not use this, so we have to add an additional value. This patch is a purely mechanical version, a more fine grained version would drop the nodes/dts files we duplicated from upstream. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | ARM: bootm: Add lower bound check of kernel in SDRAMAlexander Shiyan2020-10-281-2/+3
|/ / / | | | | | | | | | | | | | | | | | | | | | In get_kernel_addresses(), we add the lower bound check of kernel position. Kernel address cannot be lower than SDRAM start. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/sandbox' into masterSascha Hauer2020-10-141-7/+1
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| * | | of: Add common device tree register functionSascha Hauer2020-10-121-7/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | The different architectures duplicate some code around unflattening and registering the device tree. Add common functions to reduce this duplication. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/remoteproc' into masterSascha Hauer2020-10-143-0/+18
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| * | | ARM: dts: i.MX8MP: Add Cortex-M7 Coprocessor nodeSascha Hauer2020-10-072-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX8MQ has a Cortex-M7 Coprocessor. Add a node for controlling it. To make use of it the board has to provide the reserved memory nodes, for example: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; m7_reserved_sysmem1: rproc@40000000 { reg = <0 0x40000000 0 0x800000>; no-map; }; m7_reserved_sysmem2: rproc@40800000 { reg = <0 0x40800000 0 0x800000>; no-map; }; m7_reserved_sysmem3: rproc@80000000 { reg = <0 0x80000000 0 0x800000>; no-map; }; }; &remoteproc_cm7 { memory-region = <&m7_reserved_sysmem1>, <&m7_reserved_sysmem2>, <&m7_reserved_sysmem3>; }; Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: dts: i.MX8MQ: Add Cortex-M4 Coprocessor nodeSascha Hauer2020-10-071-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX8MQ has a Cortex-M4 Coprocessor. Add a node for controlling it. To make use of it the board has to provide the reserved memory nodes, for example: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; m4_reserved: m7@0x40000000 { no-map; reg = <0 0x40000000 0 0x1000000>; }; m4_reserved_sysmem3: rproc@80000000 { reg = <0 0x80000000 0 0x800000>; no-map; }; }; &remoteproc_cm4 { memory-region = <&m4_reserved>, <&m4_reserved_sysmem3>; }; Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/reboot-mode' into masterSascha Hauer2020-10-144-26/+38
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| * \ \ \ Merge branch 'for-next/magicvar-unique-id' into for-next/reboot-modeSascha Hauer2020-10-074-7/+7
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| * | | | | ARM: dts: i.MX6qdl: define BootROM reboot-mode on top of SRC_GPR{9, 10}Ahmad Fatoum2020-09-291-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SRC general purpose registers of the i.MX6 keep their values after a warm reset and are used for communication between the BootROM and upper level software. SRC_GPR9 allows software override of SRC_SBMR1, e.g. to boot via serial download protocol. Define a suitable syscon-reboot-mode node to use it. To have SRC_GPR9 take effect, bit 28 in SRC_GPR10 has to be set as well. To support this, we use the backward-compatible barebox-specific binding for having multiple 32-bit values for a single mode. This node will _not_ be fixed up into the kernel device tree due to the barebox-specific compatible, but as with all reboot mode storage, the referenced locations will be cleared to the normal (here all-zero) mode. User software that expects exclusive access to GPR9 while GPR10 bit 28 is zero will be broken. Rebooting into serial download is now possible via: barebox@board:/ gpr.reboot_mode.next=serial reset -r imxwd Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: stm32mp: remove custom reboot mode logic from arch codeAhmad Fatoum2020-09-292-26/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was ported from U-Boot to support st32mp_get_forced_boot_mode(), which allows board code to customize boot according to values the kernel places in the reboot mode region on the TAMP syscon. We no have a syscon-reboot-mode driver, a device node in the stm32mp151.dtsi, a ${global.system.reboot_mode} variable and a common reboot_mode_get(), which together achieve the same, but in a generic manner. Drop the now duplicate code. There has been no in-tree users so far, so we don't need to touch anything else. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | ARM: dts: stm32mp: setup syscon-reboot-mode on TAMP general purpose registerAhmad Fatoum2020-09-291-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the reboot mode infrastructure in place, lets add the first in-tree user. The STM32MP1 SoCs have general purpose registers in the TAMP peripheral. Register 20 there is used by the vendor's U-Boot for storing a forced boot mode. We will use the same location for our reboot mode. Consistency between barebox and OS is maintained by having barebox fixup the device tree with the same reboot mode information it used itself, so we are free to choose our own mode identifiers. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | | Merge branch 'for-next/percent_pe' into masterSascha Hauer2020-10-141-3/+2
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| * | | | | | vsprintf: retire strerrorp in favor of %peAhmad Fatoum2020-09-291-3/+2
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | strerrorp() is only used along with printf. We now have a format specifier for printing error pointers directly, so use that and remove strerrorp. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | | Merge branch 'for-next/misc' into masterSascha Hauer2020-10-1425-122/+196
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| * | | | | | ARM: stm32mp: defconfig: enable more useful optionsAhmad Fatoum2020-10-071-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve coverage by enabling more common code. Users will tweak the defconfig and cut it down anyway. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | | ARM: stm32mp: dk2: rename to dkx to make dk1 support clearerAhmad Fatoum2020-10-0710-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we now support both the stm32mp157a-dk1 and stm32mp157c-dk2 with the same barebox image, we should call the board stm32mp15xx-dkx instead. That's also how the upstream DTSI is named. Suggested-by: Holger Assmann <has@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | | ARM: stm32mp: migrate board initcalls to board driversAhmad Fatoum2020-10-073-14/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Board drivers are now the way to go. Migrate the STM32 boards to use it, to encourage future copy-pasting in following suit. As the board now supports both DK2 and DK1, rename the prefix to dkx_. dk1 specifics follow in a separate commit. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | | bootm: propagate register_image_handler return valueAhmad Fatoum2020-10-072-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While register_image_handler can't currently fail, it still returns an error code. Propagate that error code along instead of having a blanket return 0. This makes the code a little more compact. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | | commands: boot_order: note that it's OMAP specific in help textAhmad Fatoum2020-10-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kconfig and online documentation don't indicate that it's OMAP specific. Fix this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | | ARM: stm32mp: dk2: have barebox image support DK1 as wellAhmad Fatoum2020-10-022-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32MP157C-DK2 and STM32MP157A-DK1 are basically the same board except the DK2 has a MIPI-DSI display attached and the SoC has a crypto block. We can thus use the SoC type to differentiate between them and just include both device trees at tolerable 12K size increase. Cc: Holger Assmann <h.assmann@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | | ARM: stm32mp: revision: make CPU type accessible to PBLAhmad Fatoum2020-10-022-51/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is nothing holding holding us back from reading SoC type in the PBL. Migrate the necessary definitions to the header to allow for this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | | | ARM: stm32mp: init: set up CPU and bootsource at core init levelAhmad Fatoum2020-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM device tree is unflattened at core init level and banner with model extracted from device tree is printed at console init level. The only init level between is postcore, so board code seeking to modify the device tree machine model should run then. On the STM32MP1, we query SoC type at postcore initcall, so we can't have the board code fixing up the compatible on postcore as well. Resolve this by moving stm32mp_init to core_initcall. This is allowed as the code has no dependency that requires it to run postcore. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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