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| * | | ARM64: cpu: setupc: rewrite to be fully PICAhmad Fatoum2024-03-051-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code resulting from building the barebox ARM64 assembly contains relocations, which could've been position-independent just as well. Let's make them truly position independent by turning: ldr x0, =label into adr_l x0, label adr_l is position independent by virtue of being implemented using adrp, so it's usuable as-is before relocation and requires no manual addition of get_runtime_offset(). With these changes, only relocation necessary for the ARM64 generic DT 2nd stage is the one needed for get_runtime_offset() to find out whether barebox has been relocated. This is one step towards supporting mapping barebox PBL text section W^X, which precludes relocation entries emitted for code. With this change applied, there is still a data relocation entry in assembly code for get_runtime_offset(), but that doesn't bother us because it's in the data section. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240304190038.3486881-57-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: mmu-early: gracefully handle already enabled MMUAhmad Fatoum2024-03-052-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm_cpu_lowlevel_init will disable the MMU, but there are valid cases to not call it on startup, e.g. when barebox is being run as EFI payload. To allow booting an EFI-stubbed barebox both as primary bootloader and as EFI payload, teach mmu_early_enable() to bail out when the MMU is already set up. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240304190038.3486881-52-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | ARM: i.MX8MQ: fix early boot hangAhmad Fatoum2024-03-151-1/+1
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6ea731079140 ("ARM: i.MX8MQ: Streamline lowlevel startup code") changed i.MX8MQ PBL code to mimic the code introduced for later i.MX8M variants. The mimicry went a bit too far though and it exchanged i.MX8MQ boot source lookup with that of the i.MX8MN. Fix this to avoid the boot hanging with: Unhandled bootsource BOOTSOURCE_0 Fixes: 6ea731079140 ("ARM: i.MX8MQ: Streamline lowlevel startup code") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313144136.2157496-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: i.MX93 ele: fix compilationSascha Hauer2024-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | ele_call takes two arguments. The second one is removed in next where this patch was previously applied on. Add the second argument to fix compilation in master. Fixes: d27c50c131 ("ARM: i.MX93: ele: start TRNG on i.MX93 rev a1") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: i.MX93: ele: start TRNG on i.MX93 rev a1Sascha Hauer2024-03-111-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | On i.MX93 a0 the TRNG seems to be started automatically. On rev a1 it's not and OP-TEE panics with "Cannot retrieve random data from ELE". Start the TRNG to let OP-TEE startup successfully. Link: https://lore.barebox.org/20240311080624.1836184-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: rpi: fix regression booting without VideoCore DTAhmad Fatoum2024-03-051-10/+33
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Raspberry Pi firmware running prior to barebox can load a kernel directly and thus can boot barebox-dt-2nd.img straight without having to use the Raspberry Pi images. However, the Raspberry Pi specific PBL entry points, store the VideoCore DT into a handover area for earlier extraction of fixups done by the VideoCore firmware. This doesn't happen with barebox-dt-2nd.img. Commit 5ea6e19737e1 ("raspi: support to read vc values via dt-2nd boot") worked around this by using the barebox-internal DT, when a VideoCore DT wasn't saved, but this in turn added a slew of warnings to the valid setup of having no VideoCore DT at all and just using a proper Raspberry Pi PBL with their embedded DTs: WARNING: no property 'serial-number' found in vc fdt's '' node no '/system' node found in vc fdt no '/axi' node found in vc fdt no '/hat' node found in vc fdt no '/chosen/bootloader' node found in vc fdt WARNING: no property 'bootargs' found in vc fdt's '/chosen' node WARNING: no property 'overlay_prefix' found in vc fdt's '/chosen' node WARNING: no property 'os_prefix' found in vc fdt's '/chosen' node WARNING: 'pm_rsts' value not found in vc fdt ERROR: Won't delete root device node Fix this by not calling rpi_vc_fdt_parse on the barebox DT if a previous Raspberry Pi PBL has written VIDEOCORE_FDT_ERROR into the handoff area to indicate a missing VideoCore DT. Fixes: 5ea6e19737e1 ("raspi: support to read vc values via dt-2nd boot") Reported-by: Roland Hieber <rhi@pengutronix.de> Cc: Denis Osterland-Heim <denis.osterland@gmail.com> Link: https://lore.barebox.org/barebox/20240219191400.do7ib5rxy7tupv4i@pengutronix.de/ Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240305103241.2257742-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: bootm barebox: page align barebox start addressThaison Phan2024-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The aarch64 bootm image handler for barebox can choose a load address that is not 4KB aligned. This can result in unexpected behavior with the ADRP instruction that is available in 64 bit ARM architectures. ADRP forms a PC-relative address to a 4KB page where the bottom 12 bits of the current PC will be masked out. When the load address of the barebox image is not 4KB aligned ADRP can end up forming an address that starts from an invalid page of memory or the wrong page of memory that was expected to be formed. The following patch aligns the load address for the next barebox image to be 4KB aligned to accommodate the ADRP instruction. Link: https://lore.barebox.org/CAFPn3sTc_3q04koG_oPnqTmhGnejxtiva+B5KwYsCdC3czCmKw@mail.gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX93: tqm93xx: add PMIC nodeSascha Hauer2024-02-291-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | The PMIC is needs to be configured on the tqm93xx to properly reset the board, see the board specific initialisation code. We had a PMIC node in our downstream dts file which we dropped in favour for using the upstream dts. The upstream dts doesn't have a PMIC node yet, so add it again. We do not need the regulator subnodes though, as barebox doesn't support them anyway. Link: https://lore.barebox.org/20240205125301.2465254-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX: move barebox,bootsource-mmc aliases to chosen nodeSascha Hauer2024-02-278-2/+20
| | | | | | | | | | | | | | | | | | The barebox,bootsource-* properties are looked for in /chosen, not in /aliases. Move the properties to the correct node. Fixes: 7eedf79ba9 ("ARM: i.MX: add barebox,bootsource-mmc aliases") Link: https://lore.barebox.org/20240226153117.743128-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX8MP: dts: remove power domains referenced by media_blk_ctrlAhmad Fatoum2024-02-231-12/+0
|/ | | | | | | | | | | | | | | | | | | | The media_blk_ctrl is hardcoded in the DT to reference a number of power domains that we delete. The media_blk_ctrl itself is still usable without them (e.g. LVDS doesn't require ISP), but the probe in Linux would fail, because the power domain can't be attached. This has already been fixed once in commit 5600290f4bf1 ("/arch/arm/dts: imx8mp: Do not mask out mediamix power domain"), but got reintroduced recently. As the upstream DT has no ISP node and we already disable the MIPI DSI node, let's just leave the power domains untouched and see how that fares. Fixes: aaea50bbcde2 ("soc: imx: featctrl: finalize support for i.MX8MP") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220172527.599962-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/partitions'Sascha Hauer2024-02-211-0/+1
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| * default environment: make string arguments constSascha Hauer2024-02-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Change default_environment_path_set() to take a const char * and let default_environment_path_get() return a const char *. Also, do not keep a copy of the string passed to default_environment_path_set() rather than the original string to make it more clear where the path is allocated. This allows us to free the string passed to default_environment_path_set() after usage by some callers. Link: https://lore.barebox.org/20240219105507.1618465-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2024-02-2114-432/+106
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| * | ARM: Layerscape: TQMLS1046a: switch to upstream DTAhmad Fatoum2024-02-206-423/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing DT was added alongside board support in v2019.05.0. The board gained an upstream DT in Linux v6.7-rc1, which was pulled as part of v2023.12.0. So let's drop our copy to avoid duplication. This change will introduce user noticeable differences: - barebox compatible, which is also used to match kernel DT, changes - hostname changes as it's generated from DT compatible This is deemed acceptable as it aligns us with the upstream DT. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240219133340.3873032-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: dts: rpi4: add DT for CM4SPierre-Olivier Huard2024-02-163-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CM4S is close to the CM4, and thus is herited from it, with some minor changes: * The uart1 node (mini UART) does not need the clock to be forced to 500MHz. * The compatible field needs to be updated to match the CM4S There is still an issue with the dwc2 driver in timeout. Boot log: Board: Raspberry Pi Compute Module 4S IO Board deep-probe: supported due to raspberrypi,4-compute-module-s bcm2835_mci fe300000.mmc@7e300000.of: registered as mci0 WARNING: dwc2 fe980000.usb@7e980000.of: dwc2_core_reset: Timeout! Waiting for Core Soft Reset ERROR: dwc2 fe980000.usb@7e980000.of: probe failed: Connection timed out bcm2835_mci fe340000.mmc@7e340000.of: registered as mci1 malloc space: 0x1f17ca80 -> 0x3e2f94ff (size 497.5 MiB) no /dev/disk0.0 or /dev/mmc0.0. using default env no '/hat' node found in vc fdt environment load /dev/env0: No such file or directory Maybe you have to create the partition. Hit any to stop autoboot: 3 Signed-off-by: Pierre-Olivier Huard <pierre-olivier.huard@rtone.fr> Link: https://lore.barebox.org/20240215120109.23242-1-pierre-olivier.huard@rtone.fr Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: at91: sama5d27-som1: autoping watchdog during barebox runtimeAhmad Fatoum2024-02-134-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BootROM arms the watchdog with the maximum timeout of 16 seconds on boot. This is ample time to boot into Linux userspace, so so far we didn't touch the watchdog for the SAMA5D2 in barebox and expected the user to disable the watchdog manually, e.g. via the `wd -x` command or by storing nv.autoboot=abort into the environment. While this works, this is admittedly bad user experience, so let's just enable watchdog polling in barebox instead. That way, we still have watchdog supervision, but don't reset when dropping into the barebox shell. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240212154617.2260448-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | eth: replace ethaddr_to_string() with %pMSascha Hauer2024-02-052-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | Now that we can print MAC addresses using the %pM format specifier we can get rid of ethaddr_to_string(). Do this treewide. Link: https://lore.barebox.org/20240202151147.226876-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2024-02-2129-1026/+2041
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| * | | ARM: i.MX: add barebox,bootsource-mmc aliasesSascha Hauer2024-02-209-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several boards overwrite the standard mmc aliases to give them a board specific numbering. This breaks our assumption that the bootsource instance number matches the mmc alias numbering. barebox supports barebox,bootsource-mmc aliases to provide a mapping between the bootsource and the device nodes that provides them. Add these aliases for the newer i.MX SoCs. Link: https://lore.barebox.org/20240220104402.2475000-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | hab: implement i.MX9 supportSascha Hauer2024-02-161-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the underlying architecture of AHAB is quite different than HAB, the user interface fits into the existing hab command quite well, so integrate it into the existing HAB infrastructure. Link: https://lore.barebox.org/20240213151744.307958-7-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: ele: implement more ELE operationsSascha Hauer2024-02-161-1/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements more ELE operations useful for AHAB secure boot. Link: https://lore.barebox.org/20240213151744.307958-6-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: bbu: fix i.MX9 eMMC boot bbu handlerSascha Hauer2024-02-131-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX9 eMMC boot bbu handler does not work currently, because the code expects a i.MX image which is not what we need on i.MX9. The code is also full of i.MX image specific quirks which we don't need on i.MX9, so use the just created imx_bbu_internal_mmcboot_register_handler() for i.MX9. Link: https://lore.barebox.org/20240208075217.697668-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | bbu: create a standard bbu handler for eMMC bootSascha Hauer2024-02-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a standard bbu handler to be used when an update is just a matter of writing an image to the eMMC boot partitions. As these may also want to set the BBU_FLAG_MMC_BOOT_ACK flag, it is moved up one level to struct bbu_handler::flags to make it configurable when struct bbu_data is not yet instantiated. Link: https://lore.barebox.org/20240208075217.697668-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: tqma93xx: Add LGA board variantSascha Hauer2024-02-138-41/+1596
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LGA variant needs different DDR setup and another device tree. The board type can be read from EEPROM, so we don't need another image for it. Link: https://lore.barebox.org/20240205074553.2005284-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX9: rename TQ i.MX93 board to TQMA93XXSascha Hauer2024-02-139-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TQ i.MX93 boards come in different variants, all of which can be identified with an EEPROM. We can support all variants in a single image, so rename the tqmba9xxxca, which is only one variant, to TQMA93XX which can be used as a name covering all variants. Link: https://lore.barebox.org/20240205074553.2005284-8-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX93: tqma9352-mba93xxca: use upstream device treeSascha Hauer2024-01-301-787/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tqma9352-mba93xxca device tree went upstream, so switch to the upstream version. This is currently nearly identical to our downstream version, only the PMIC node is not yet in upstream, but we don't need this for barebox. Link: https://lore.barebox.org/20240124085146.2308724-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX8M: convert the machine init to the soc driverMarco Felsch2024-01-293-140/+10
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the i.MX8M machine init code to the previously introduced soc framework. The soc driver was mostly copied from Linux with slightly adaptions for barebox. To the soc driver is called during the postcore_initcall to keep the level aligned with the previous imx_init(). The ocotp clock must keept running else the ARM-SMCCC stuck for calls where the TF-A tries to access the ocotp. A sample output of the new introduced soc0 device: | | barebox@FSL i.MX8MM EVKB:/ devinfo soc0 | Bus: soc | Parameters: | family: Freescale i.MX (type: string) | machine: FSL i.MX8MM EVKB (type: string) | revision: 1.0 (type: string) | serial_number: 15182A09DAB5B3C9 (type: string) | soc_id: i.MX8MM (type: string) Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20240125133856.3792552-2-m.felsch@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | / clk: at91: sync drivers with LinuxAhmad Fatoum2024-02-161-1/+14
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During bug hunt of a clocking issue that ultimately turned out to be unrelated, I resynced AT91 clk support with Linux. The changes look more extensive than they really are, because I first imported the clock drivers before a major overhaul of the barebox clock framework to be more compatible with the more recent kernel API changes. Most of the diff is due to that, but this resync also fixes at least a USB issue for the at91rm9200 and adds support for the new SAMA7 SoC as well as more clocks for the SAM9x60. Both these SoCs aren't supported by barebox yet, but this at least adds clock driver support. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240215121837.251013-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX: add Kconfig option for scratchmemSascha Hauer2024-02-082-1/+6
| | | | | | | | | | | | | | | | | | | | scratch.c is needed for both i.MX8 and i.MX9, but is compiled only for i.MX8, so linking will failed if only i.MX9 is enabled. Add a Kconfig option for it and select it from both i.MX8 and i.MX9. Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20240205125728.2470228-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX defconfigs: Enable ELE nvmem supportSascha Hauer2024-02-052-0/+2
|/ | | | | | | | | The ELE nvmem support is needed on i.MX9 for reading fuses, especially for reading MAC addresses from the fuses. Enable it in the relevant defconfigs. Link: https://lore.barebox.org/20240131083446.673104-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2024-01-238-26/+7
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| * clk: select CLKDEV_LOOKUP from COMMON_CLKAhmad Fatoum2024-01-195-18/+0
| | | | | | | | | | | | | | | | | | | | All platforms that select COMMON_CLK also select CLKDEV_LOOKUP, therefore just select it in drivers/clk/Kconfig and drop the CLKDEV_LOOKUP all over the place. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240118090718.1314156-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: make COMMON_CLK a visible symbolAhmad Fatoum2024-01-193-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far, we expected platforms to select COMMON_CLK if they have a clock controller that's covered by the common clk framework and HAVE_CLK if they have a legacy clock driver. With the addition of SCMI clocks, platforms, especially virtualized ones, that previously didn't need clock support may now want access to them. Instead of having to select COMMON_CLK from such platforms on the off-chance that SCMI clocks may need to be used, just make COMMON_CLK user visible, so it can be selected as needed. As COMMON_CLK needs to conflict with legacy clock support, we also add a symbol for that and start selecting it where appropriate, Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240118090718.1314156-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * pbl/pmic.h: rename pmic_reg_write() to pmic_reg_write8()Sascha Hauer2024-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | pmic_reg_write() does 8 bit writes, so rename the function accordingly. When adding 16/32 bit writes there is no point in abstracting the register width in pmic_reg_write(), because the caller actually must know the register width to make useful register changes. This means we better add pmic_reg_write16/32 when need arises. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/layerscape'Sascha Hauer2024-01-2336-169/+1652
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| * | ARM: layerscape: enable DWC3 snooping on ls1046aAhmad Fatoum2024-01-111-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SCFG_SNPCNFGCR USB bits only have an effect if the Layerscape-specific bits in each DWC instance's GSBUSCFG0 are appropriately configured. As the LS1046's kernel DT is configured to assume the whole SoC is dma-coherent, we need to set these bits, so this is indeed the case. This configuration is likewise applicable to the LS1043A, should we add support for it and to the newly added LS1028A, if we start configuring the CCI-400 to make the fully cache-coherent, but alas, that's not yet the case and the LS1028A's kernel DT doesn't assume it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240110160112.4134162-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: layerscape: configure all DMA masters to be cache-coherentAhmad Fatoum2024-01-113-25/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upstream device tree now has /soc/dma-coherent, which breaks USB in Linux v6.1 when kernel is booted with barebox. Fix this by: - setting the snoop bits for the DMA masters, so we properly support Linux >= v6.1 DTs - fixing up cache coherency setting into kernel DT whenever barebox DT has /soc/dma-coherent to support older device trees The latter is done automatically when OF_DMA_COHERENCY is selected, so add the missing snoop bits here. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240110160112.4134162-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: dts: layerscape: mark ls1046a SoC DMA incoherent in DTAhmad Fatoum2024-01-111-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This effectively reverts in the barebox DT, Linux commit 136975c33894 ("arm64: dts: ls1046a: make dma-coherent global to the SoC"). The reason for that is while the CCI-400 can be configured to make all bus masters DMA-coherent, barebox (and older versions of U-Boot) didn't yet do so. We will rectify this in a later commit, but for now restore working order in case Linux is booted with the barebox DT. Fixes: 32e2176ba050 ("dts: update to v6.1-rc1") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240110160112.4134162-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: dts: layerscape: add header for barebox DT overridesAhmad Fatoum2024-01-113-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't use the ls1046a-rdb kernel device tree as-is for barebox, but instead include it and override some nodes. Some overrides can be applicable to all SoCs so add a new file that's ls1046a-specific. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240110160112.4134162-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Layerscape: add basic support for NXP LS1028a RDBSascha Hauer2024-01-1011-3/+317
| | | | | | | | | | | | | | | | | | | | | | | | The NXP LS1028a RDB is a LS1028a Eval board. Currently supported are SD/MMC, ethernet and SD image generation. Link: https://lore.barebox.org/20240109161527.3237581-22-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Layerscape: LS1028a: implement bootsource detectionSascha Hauer2024-01-102-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | Detecting the bootsource is just a matter of decoding the porsr1 register. Implement it. Link: https://lore.barebox.org/20240109161527.3237581-19-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: multi_v8_defconfig: disable CONFIG_MCI_STARTUPSascha Hauer2024-01-101-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | SD/eMMC cards are detected automatically when needed for environment or barebox_update, so do not probe them during registration. Link: https://lore.barebox.org/20240109161527.3237581-17-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: enable Layerscape boards in multi_v8_defconfigSascha Hauer2024-01-101-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Now that Layerscape can do MULTIARCH enable the Layerscape boards in multi_v8_defconfig. Link: https://lore.barebox.org/20240109161527.3237581-16-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Layerscape: move over to MULTIARCHSascha Hauer2024-01-101-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | Layerscape doesn't contain any unprotected initcalls anymore, so we can safely move it over to MULTIARCH. Link: https://lore.barebox.org/20240109161527.3237581-15-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Layerscape: LS1028a: add psci nodeSascha Hauer2024-01-102-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The upstream dts files do not contain a psci node. Add one in order to use PSCI to reset the system. This will also add a PSCI node to the dtb the kernel is started with so that the Kernel can use PSCI to bring up the secondary CPU core. Link: https://lore.barebox.org/20240109161527.3237581-14-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: psci: make header self containedSascha Hauer2024-01-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | arch/arm/include/asm/psci.h uses struct device_node, so declare it in order to make the file self contained. Link: https://lore.barebox.org/20240109161527.3237581-13-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Layerscape: LS1028a: fixup icidsSascha Hauer2024-01-102-0/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA operations from peripherals have a stream id attached to them which must match the stream ids configured in the IOMMU. Configure the stream ids in the peripheral registers and fixup the Kernel device tree with the configured stream ids. The code is based on the corresponding U-Boot code as of U-Boot-2023.10-rc1. The result is hard to match against the U-Boot code though as U-Boot hides the initialisation arrays behind multiply layered defines which are dropped here to make the code readable. Link: https://lore.barebox.org/20240109161527.3237581-12-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Layerscape: icid: factor out setup_icid_offsets()Sascha Hauer2024-01-101-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | The code to iterate over the icid table writing register values can be re-used for upcomin LS1028a support, so move the code to a separate function. Link: https://lore.barebox.org/20240109161527.3237581-10-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Layerscape: icid: use of_property_write_u32_array() in ↵Sascha Hauer2024-01-101-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_set_qportal_iommu_prop() Use of_property_write_u32_array() rather than of_set_property() to make the code a bit clearer. Link: https://lore.barebox.org/20240109161527.3237581-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Layerscape: icid: use of_property_write_u32_array() in of_set_iommu_prop()Sascha Hauer2024-01-101-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Use of_property_write_u32_array() rather than of_set_property() to make the code a bit clearer. Link: https://lore.barebox.org/20240109161527.3237581-8-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-19 12:30:50 +0000