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* ARM: rockchip: fix iodomain for r2pro V1.0HEADmasterFrank Wunderlich4 hours2-3/+9
| | | | | | | | | | | | | Current code sets vccio4 and vccio6 both to 1v8. R2Pro v1.0 needs 3v3 setting on vccio4, else gmac0 (switch for lan-ports) will be damaged. IO-domain is per default 3v3 so only vccio6 needs to be set to 1v8 and clear this bit in the 3v3 register. Fixes: 8ba96c5942d6 ("ARM: rockchip: add BPI-R2-Pro V00 board") Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.barebox.org/20220514155609.8306-1-linux@fw-web.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx: esdctl: fix LPDDR4 size calculationLucas Stach5 hours1-1/+1
| | | | | | | | | | | | | The DDRC only uses the DEVICE_CONFIG field for memory types other than LPDDR4. While LPDDR4 always has a bus width of x32, the script aid generates the value for a x16 bus, as this was apparently used for the controller validation. This resulted in the calculated DRAM size to be halved on boards with LPDDR4 memory. Fixes: d8d5778ee8c2 ("ARM: imx: Correct mem size calculation for 4/8/16/32 bit bus width") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.barebox.org/20220513141625.1411217-1-l.stach@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX7: esdctl: fix out-of-bounds read on memory size calculationAhmad Fatoum5 hours1-3/+5
| | | | | | | | | | | | addrmap[] has 9 elements on i.MX8M platforms and 7 elements on i.MX7. Checking unconditionally for addrmap[8] is thus out-of-bounds on the i.MX7. Get both arrays to the same size to fix this. This is ok, because an addrmap of 0 is a no-op. Fixes: 42d45ef380c5 ("ARM: imx: Add imx8 support for SDRAM with two or more bank groups") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220513135352.2061026-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: karo-tx6x: Fix DCD check operationsSascha Hauer13 days4-36/+35
| | | | | | | | | | | | | | | | | In f04deb4018 was discovered that we used the wrong names for the check operations. What we named "while_all_bits_clear" really was the operation "until_all_bits_clear" and likewise for the other operations, so this patch renamed the operations from "while_*" to "until_*". Additionally it was assumed that the users have the correct textual logic, but were compiled to the wrong result. At least for the Karo TX6X boards it was the other way round though: The texts were wrong, but the result was correct. This means, although they had the wrong text, the result was working on the hardware. Now f04deb4018 replaced "while_all_bits_clear" with "until_all_bits_set" and with this broke the DCD tables. Fix this by replacing them with the correct commands. Fixes: f04deb4018 ("i.MX/DCD compiler and interpreter: logic is different") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: rpi: fix CM3 breakage after multi-image reworkAhmad Fatoum13 days2-4/+29
| | | | | | | | | | | | | | | | | | | | | | barebox used to apply quirks by asking VideoCore firmware. If this was not possible, an error message is printed, but other initialization happened as expected. With the move to board driver matched by DT, we incur two breakages: - Compute Module 3/3+ used to be explicitly supported, but are absent in new compatible list - Unsupported variants used to initialize with only an error message, but now their revision ID must be known Fix this by amending the compatible list with all non-Raspberry Pi 4 compatibles listed in the binding. We also make existence of a match data optional and error out if it doesn't exist. This is so far unused, but it conveys the intent for future users. Fixes: c062cd5cf47d ("ARM: rpi: validate devicetree compatible instead of changing model name") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220502142959.1325298-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clocksource: assign non-zero priorities to all clocksourcesAhmad Fatoum2022-04-259-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most barebox clocksources have a zero priority and if multiple of them exist, but no higher priority ones, the first to call init_clock wins. Some supported boards like the Raspberry Pi additionally depended on initcall ordering to favor one zero-priority clocksource over another. With the move to deep probe and with Commit b641580deb8c ("of: platform: Ensure timers are probed early"), device tree blob iteration order could now dictate which clocksource is ultimately used. This led to a 20 times slower clock source being chosen on the Raspberry Pi, because the ARM architected timer was taken instead of the bcm2835 timer. Fix the root cause by assigning priorities to all clocksource drivers. Priorities chosen are: 50: device_initcall 60: coredevice_initcall 70: postcore_initcall 80: core_initcall These priorities are all below 100, which was previously the lowest positive priority and as they are positive, they win against the dummy clocksource. This should ensure no priority inversion happens. Fixes: b641580deb8c ("of: platform: Ensure timers are probed early") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220425094857.674044-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: asm: fix miscompilation of 32-bit ENTRY_FUNCTION_WITHSTACKAhmad Fatoum2022-04-251-1/+13
| | | | | | | | | | | | | | | | | | | | | | gcc-11.1.1 shipped with OSELAS.Toolchain-2021.07.0 hoists a single instruction from __ARM_SETUP_STACK in front of __barebox_arm_head breaking the barebox header format for the Raspberry Pi 3. This can't happen with ARM64 and the Raspberry Pi entry points are currently the only 32-bit users. While the resulting barebox image was still bootable, header detection would fail. Add an intermediate naked function for arm32 to work around this. This is not required for plain ENTRY_FUNCTION, because the board-supplied entry point is already NAKED. For ENTRY_FUNCTION_WITH_FUNCTION, that naked entry point is moved to arch code intentionally to reduce pitfalls for board code authors.. Fixes: 880c9803b95a ("ARM: implement ENTRY_FUNCTION_WITHSTACK") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220425094857.674044-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32'Sascha Hauer2022-04-211-5/+0
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| * ARM: dts: stm32mp: remove no-longer required DT overrideAhmad Fatoum2022-03-281-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | These same properties have been available in the upstream DT since Linux commit c9669b4692ce ("ARM: dts: stm32: add usbphyc vdda1v1 and vdda1v8 supplies on stm32mp151") imported to barebox with commit f826d85b7ab0 ("dts: update to v5.12-rc1"). They can thus be safely dropped now. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220322132545.227838-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2022-04-214-151/+21
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| * | ARM: Rockchip: Update DTS for BPI-R2Pro for new HW-RevFrank Wunderlich2022-04-141-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New Hardware revision swapped the gmacs (wan is now gmac1). Previous Revision (v00) was not in public sale so devicetree can be safely changed. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.barebox.org/20220411114447.20488-1-linux@fw-web.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: dts: at91-microchip-ksz9477-evb: start using kernel DTOleksij Rempel2022-04-121-136/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This DT is mainlined to the kernel. Now we can start using kernel version. At same time it will fix SPI and KSZ switch detection. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.barebox.org/20220407085933.952078-1-o.rempel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: fix GCC 11.x build failures for ARMv7Ian Abbott2022-04-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building barebox for ARMv7 with GCC 11.x results in errors similar to the following: CC common/state/state_variables.o {standard input}: Assembler messages: {standard input}:1535: Error: selected processor does not support `rev r3,r3' in Thumb mode {standard input}:1576: Error: selected processor does not support `rev r3,r3' in Thumb mode Or: CC common/state/state_variables.o {standard input}: Assembler messages: {standard input}:1405: Error: selected processor does not support `rev r3,r3' in ARM mode {standard input}:1453: Error: selected processor does not support `rev r3,r3' in ARM mode The problem is that the compiler option `-march=armv7-a` is not being chosen by "arch/arm/Makefile", but rather the fallback options `-march=armv5t -Wa,-march=armv7-a` are being chosen. Appending `-msoft-float` to `KBUILD_CPPFLAGS` earlier in "arch/arm/Makefile" before the tests for supported `-march` options seems to fix the problem. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Link: https://lore.barebox.org/20220408170154.114526-1-abbotti@mev.co.uk Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: asm: setjmp: add missing .pop_sectionAhmad Fatoum2022-03-281-0/+1
| |/ | | | | | | | | | | | | | | | | This fixes a mismatched .push_section. This had no effect, because the file ended after the follow-up .push_section. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Link: https://lore.barebox.org/20220319074335.1313872-1-ahmad@a3f.at Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2022-04-2110-23/+772
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| * | ARM: pbab01: allow USB-OTG port runtime configurationAndrej Picej2022-04-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit a5a4c1d5a3 ("dts: update to v5.13-rc1"), which synced kernel dts, USB-OTG port on phyFLEX board was set to work only in peripheral mode. This has to do with phyFLEX baseboard hardware bug, which prevents correct USB OTG ID pin detection in kernel code. Unlike linux kernel, barebox doesn't support OTG auto-detection mode via ID pin. In barebox, user has to select desired USB mode of operation by setting 'otg.mode' variable. Thus set the 'dr_mode' property to "otg" to be able to later select USB OTG operating mode at runtime (either host or peripheral). Signed-off-by: Andrej Picej <andrej.picej@norik.com> Link: https://lore.barebox.org/20220419124659.257134-1-andrej.picej@norik.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: CCMX51: Add support for 16-bit memory module variantsAlexander Shiyan2022-04-203-2/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | Modules can have memory chips with a bus width of 16 bits. Let's separate the binaries for initializing different types. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Link: https://lore.barebox.org/20220419072123.28590-3-eagle.alexander923@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: CCMX51: Add support for low-level debugAlexander Shiyan2022-04-201-0/+28
| | | | | | | | | | | | | | | | | | Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Link: https://lore.barebox.org/20220419072123.28590-2-eagle.alexander923@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: CCMX51: Remove excess assignmentAlexander Shiyan2022-04-201-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Default assignment for board index is already done in array initialization. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Link: https://lore.barebox.org/20220419072123.28590-1-eagle.alexander923@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: boards: protonic-imx6: fix file system access warningOleksij Rempel2022-04-011-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should not access a file system from the poller. So, do it from the worker. This patch will fix warning on FS access for Protonic board code. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.barebox.org/20220328120956.2402132-1-o.rempel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: boards: protonic-imx6: properly configure RGMII direction for the FEC MACOleksij Rempel2022-03-281-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | To make SJA1105 switch work properly with bareobx, we need to configure RGMII ref_clk. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.barebox.org/20220321092103.1357659-2-o.rempel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: boards: protonic-imx6: add board specific BBU SD handlersOleksij Rempel2022-03-281-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | Add barebox update handler for the SD ports. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.barebox.org/20220321092103.1357659-1-o.rempel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: webasto-marvel: share the run-time setup with the ccbv2 variantJuergen Borleis2022-03-282-7/+23
| | | | | | | | | | | | | | | | | | Signed-off-by: Juergen Borleis <jbe@pengutronix.de> Link: https://lore.barebox.org/20220321140856.59479-3-jbe@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: webasto-marvel: add device tree shared with the kernelJuergen Borleis2022-03-282-0/+587
| | | | | | | | | | | | | | | | | | Signed-off-by: Juergen Borleis <jbe@pengutronix.de> Link: https://lore.barebox.org/20220321140856.59479-2-jbe@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: webasto-ccbv2: consider the available memory size for opteeJuergen Borleis2022-03-281-4/+4
| |/ | | | | | | | | | | Signed-off-by: Juergen Borleis <jbe@pengutronix.de> Link: https://lore.barebox.org/20220321140856.59479-1-jbe@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: omap: Fix linker error with MTD disabledSascha Hauer2022-04-211-0/+5
| | | | | | | | | | | | | | We are using mtd functions now, make sure we do so only with MTD enabled to prevent linker errors. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: omap: xload: read from unpartitioned deviceSascha Hauer2022-04-211-53/+33
|/ | | | | | | | | | | | The omap xload code creates a temporary partition where the barebox image is read from. Since 7f9f45b9bf it is no longer allowed to create overlapping partitions which means the temporary partition can no longer be created when the device was partitioned already. Fix this by using the mtd PEB api to read the barebox image from the full device and not from a partition. Fixes: 7f9f45b9bf ("devfs: Do not create overlapping partitions") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32'Sascha Hauer2022-03-1420-32/+605
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| * ARM: stm32: add support for PHYTEC phyCORE stm32mp1Steffen Trumtrar2022-03-089-0/+463
| | | | | | | | | | | | | | | | | | | | | | | | Import DT[1] and add the boilerplate to have barebox generate a SSBL for the board. [1]: git://git.phytec.de/tf-a-stm32mp Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220302160242.2997946-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: ddrctl: add STM32MP131 RAM size querying supportAhmad Fatoum2022-03-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | buswidth is read from HW. With nb_bytes == 2, there is a possibility that we get a zero size out here, if driver and device are mismatched, e.g. because barebox is booted in FIP with mismatched external device tree. As this runs very early before relocation, round up instead of crashing to be a bit more on the safe side. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220223113846.3022227-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: add board support for STM32MP135F-DKAhmad Fatoum2022-03-087-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We already have the needed drivers in place to support the upcoming STM32MP131. Linux already has a basic DT for the DK board. Add a barebox board that leverages it. To try it out modify the existing FIP with: fiptool update --nt-fw build/images/barebox-stm32mp-generic-bl33.img \ --hw-config build/arch/arm/dts/stm32mp135f-dk.dtb \ mmcblk0p3 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220221103625.3728055-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: ddrctl: add STM32MP131 RAM size querying supportAhmad Fatoum2022-03-082-7/+27
| | | | | | | | | | | | | | | | | | Full buswidth for STM32MP131 means 2 byte wide, not 4 as the memory bus is restricted to 16-bit. Teach barebox the difference. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220221103625.3728055-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: enable more config optionsAhmad Fatoum2022-03-081-1/+7
| | | | | | | | | | | | | | | | | | We have recently gained SCMI and LTDC support as well as a new SPI display. Enable them in the defconfig. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-25-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: dts: stm32mp: remove regulator-name override in stm32mp151.dtsiAhmad Fatoum2022-03-081-4/+0
| | | | | | | | | | | | | | | | | | barebox regulator core will now just take node name in absence of the property, so no need for this fixup any longer. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-24-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: smccc: sync header with upstreamAhmad Fatoum2022-02-231-0/+17
| | | | | | | | | | | | | | | | | | For upcoming SCMI over SMC support, we'll need a newer version of the header. Import it from v5.13-rc1. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: ddrctrl: fix wrong register field widthsAhmad Fatoum2022-02-231-5/+5
| | | | | | | | | | | | | | | | | | Consulting the reference manual shows that column fields are 4 bits each, but some of them were treated as 5-bit wide. Fix it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-9-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: build extra barebox-stm32mp-generic-bl33.imgAhmad Fatoum2022-02-232-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | barebox-dt-2nd.img expects being loaded at an offset, so the stack can grow down from entry point. The STM32MP TF-A default is to not have an offset. Avoid this issue by having a stm32mp specific entry point that sets up a 64 byte stack after end of barebox. As it's stm32mp-specific anyway, we can skip the early FDT parsing and ask the SDRAM controller about RAM size. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: change stm32image extension to .stm32Ahmad Fatoum2022-02-231-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The .img extension for stm32mp1 images is unfortunate. The format is deprecated and its header makes it not directly executable and thus not suitable as-is for use in a FIP image where the BL33 is run from offset 0. To make existence of the STM32 header evident, rename the extension from .img to .stm32. As it's still supported by TF-A, have symlinks, so user build script can use the old names for now. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * pinctrl: stm32: use gpio-ranges instead of aliasAhmad Fatoum2022-02-231-12/+0
| | | | | | | | | | | | | | | | | | | | Upstream device tree doesn't feature aliases and we don't really need it, as the gpio-ranges property has a GPIO controller offset cell. Use it instead. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/of-deep-probe'Sascha Hauer2022-03-1411-18/+18
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| * | of: rename of_find_node_by_name() to of_find_node_by_name_address()Sascha Hauer2022-03-0811-18/+18
| |/ | | | | | | | | | | | | | | | | | | | | | | | | of_find_node_by_name() has the same name as the corresponding kernel function but a different semantics. A node name is comprised of the nodes name and a unit address, separated with '@'. Linux of_find_node_by_name() matches only the name before the '@' whereas the barebox function compares the full name. As several callers depend on the barebox semantics we can't just change the semantics, so rename the barebox function to of_find_node_by_name_address(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2022-03-141-0/+12
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| * | arch: arm: mach-imx: document field return in CSF templateBastian Krause2022-02-281-0/+12
| |/ | | | | | | | | | | | | | | | | | | Activating the field return configuration returns a locked-down board (nearly) to its open state. In order to burn the FIELD_RETURN fuse, the CSF must contain a specific unlock command with the device's UID. Signed-off-by: Bastian Krause <bst@pengutronix.de> Link: https://lore.barebox.org/20220225100344.4166248-1-bst@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX: Remove duplicate PFD workaroundSascha Hauer2022-03-081-44/+0
| | | | | | | | | | | | | | | | | | | | The i.MX6Q and i.MX6D SoC variants need a workaround for broken PFDs. That was added to the architecture code in f1f6d76 ("ARM: i.MX6: correct work flow of PFDs from uboot-sources") and then added again in b534f79 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK"). We only need this once, so remove the workaround in the architecture code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX6: configure AIPS3 for i.MX6ULL/i.MX6SXAhmad Fatoum2022-03-042-0/+15
| | | | | | | | | | | | | | | | | | UltraLiteLite and SoloX both have an AIPS3, which has e.g. RNGB on it. COnfigure that likewise to AIPS1 and AIPS2. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220303144246.3603311-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX: factor out AIPS configuration into helper functionAhmad Fatoum2022-03-041-21/+23
| | | | | | | | | | | | | | | | | | | | We have the exact same sequence twice for each AIPS and i.MX6ULL/SX add another AIPS, so it's time to factor this out into a dedicated helper function and comment it a bit more. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220303144246.3603311-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: arch: dts: qspi: Add QSPI config to the NXP IMX8MN-EVK boardJoacim Zetterling2022-03-032-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add QSPI support in the default config and DTS files for the NXP IMX8MN-EVK board. To be able to use it You also need the QSPI driver enabled. Tested on the NXP IMX8MN-EVK board as well as on an IMX8MN custom bord supporting a QSPI flash. Tested with the memory dump command i.e. 'md -s /dev/m25p0'. Signed-off-by: Joacim Zetterling <joacim.zetterling@westermo.com> Link: https://lore.barebox.org/20220301132308.343496-1-joacim.zetterling@westermo.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: imx: Correct bit count functionJoacim Zetterling2022-02-281-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | Correct the imx_ddrc_count_bits which currently did a wrong bit check (stopped after the first check). Tested on a IMX8MN Evk with 2GB DDR4 and on a IMX8MN custom board with 512MB LPDDR4, checked size and made memory test. Signed-off-by: Joacim Zetterling <joacim.zetterling@westermo.com> Link: https://lore.barebox.org/20220225144751.4160843-5-joacim.zetterling@westermo.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: imx: Correct mem size calculation for 4/8/16/32 bit bus widthJoacim Zetterling2022-02-281-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The imx8mn has a 16-bit SDRAM bus width access but the calculation of the memory size treat it as a 32-bit width bus which makes the memory calculation to be wrong (meminfo wrong and memtest fails). There is a difference between the imx7 and the imx8 familys. The imx8 family has a device config field in the master register of the DDRC controller which the imx7 family doesn't have (the bus width is 32-bit as default). The device config field together with the DQ configuration tells us the actual bus width of the device for a correct mem size calculaton. >From the imx8mn reference manual: +----------------------------------------------------+ | Field | Function | |----------------------------------------------------| | 31-30 | Indicates the configuration of the | | | device used in the system. | | device_config | 00b - x4 device | | | 01b - x8 device | | | 10b - x16 device | | | 11b - x32 device | +----------------------------------------------------+ ... ... The imx8 supports a bus width of 4 bits or x4 (device_config b00). This is a problem for the calculation of the mem size when it only handle the bus width in bytes. Therefore we must treat the mem size calculation for the half bus width (width = 0) in a special way. Do the calculation with one byte width and then divide the mem size by 2 later on. Signed-off-by: Joacim Zetterling <joacim.zetterling@westermo.com> Link: https://lore.barebox.org/20220225144751.4160843-4-joacim.zetterling@westermo.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: imx: Add imx8 support for SDRAM with two or more bank groupsJoacim Zetterling2022-02-281-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Add bank group size to handle SDRAM with two or more bank groups in one chip. The imx8mn DDR4 has one mem chip with ranks set to 1 and the number of banks is 4 in 2 groups, total of 8 banks. We need two add the DDRC_ADDRMAP8 and do a check DDRC_ADDRMAP8_BG_B0 and DDRC_ADDRMAP8_BG_B1 to get the number of bank groups in the chip. Signed-off-by: Joacim Zetterling <joacim.zetterling@westermo.com> Link: https://lore.barebox.org/20220225144751.4160843-3-joacim.zetterling@westermo.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>